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    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    1.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20210327892A1

    公开(公告)日：2021-10-21

    申请号：US17360349

    申请日：2021-06-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Euntaek JUNG ,  JoongShik SHIN ,  Dongyoun SHIN

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11519

    Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including a plurality of gate electrodes sequentially stacked on the substrate in a first direction that extends perpendicular to an upper surface of the substrate, a source conductive pattern between the substrate and the electrode structure, a vertical semiconductor pattern penetrating the electrode structure and the source conductive pattern, and a data storage pattern extending in the first direction between the vertical semiconductor pattern and the electrode structure. A lower surface of the data storage pattern contacts the source conductive pattern. A portion of the lower surface of the data storage pattern is at a different height from the upper surface of the substrate, in relation to a height of another portion of the lower surface of the data storage pattern from the upper surface of the substrate.

    MEMORY DEVICE
    3.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20220367513A1

    公开(公告)日：2022-11-17

    申请号：US17878304

    申请日：2022-08-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungmin SONG ,  Beyounghyun KOH ,  Yongjin KWON ,  Kangmin KIM ,  Jaehoon SHIN ,  JoongShik SHIN ,  Sungsoo AHN ,  Seunghwan LEE

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157

    Abstract: A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.

    MEMORY DEVICE
    4.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20210111188A1

    公开(公告)日：2021-04-15

    申请号：US16895364

    申请日：2020-06-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungmin SONG ,  Beyounghyun KOH ,  Yongjin KWON ,  Kangmin KIM ,  Jaehoon SHIN ,  JoongShik SHIN ,  Sungsoo AHN ,  Seunghwan LEE

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565

    Abstract: A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    6.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20190333922A1

    公开(公告)日：2019-10-31

    申请号：US16152605

    申请日：2018-10-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Euntaek JUNG ,  JoongShik SHIN ,  Dongyoun SHIN

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157

    Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including a plurality of gate electrodes sequentially stacked on the substrate in a first direction that extends perpendicular to an upper surface of the substrate, a source conductive pattern between the substrate and the electrode structure, a vertical semiconductor pattern penetrating the electrode structure and the source conductive pattern, and a data storage pattern extending in the first direction between the vertical semiconductor pattern and the electrode structure. A lower surface of the data storage pattern contacts the source conductive pattern. A portion of the lower surface of the data storage pattern is at a different height from the upper surface of the substrate, in relation to a height of another portion of the lower surface of the data storage pattern from the upper surface of the substrate.

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190325939A1

    公开(公告)日：2019-10-24

    申请号：US16502943

    申请日：2019-07-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JoongShik SHIN ,  Byoungil LEE ,  Hyunmog PARK ,  Euntaek JUNG

    IPC: G11C11/408 ,  G11C11/06 ,  G11C8/12 ,  G11C8/08 ,  H01L27/11582 ,  H01L21/8239 ,  H01L27/11573 ,  H01L27/11565 ,  G11C8/14 ,  H01L23/528 ,  H01L27/11575

    Abstract: A semiconductor memory device includes a substrate, a ground selection line, a word line, an insulating layer, a vertical channel portion, and a first peripheral circuit gate pattern. The substrate includes a cell array region and a peripheral circuit region. The ground selection line is on the cell array region. The word line is on the ground selection line. The insulating layer is between the ground selection line and the word line. The vertical channel portion penetrates the ground selection line, word line, and insulating layer in a direction vertical to a top surface of the substrate. The first peripheral circuit gate pattern is on the peripheral circuit region of the substrate. The insulating layer extends from the cell array region onto the peripheral circuit region to cover a top surface of the first peripheral circuit gate pattern.

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