公开(公告)号：US09191599B2

公开(公告)日：2015-11-17

申请号：US13778591

申请日：2013-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yu-Jin Park ,  Kyo-Jin Choo ,  Ji-Hun Shin ,  Ji-Min Cheon ,  Jin-Ho Seo ,  Seog-Heon Ham

IPC: H04N5/335 ,  H04N5/00 ,  H04N5/378 ,  H04N5/357

CPC classification number: H04N5/378 ,  H04N5/3575

Abstract: A correlated double sampling (CDS) circuit included in an image sensor includes a sampling unit and a timing controlled band-limitation (TCBL) unit. The sampling unit is configured to generate an output signal by performing a CDS operation with respect to a reset component of an input signal and an image component of the input signal based on a ramp signal, the input signal being provided from a pixel array included in the image sensor. The TCBL unit is connected to the sampling unit, and is configured to remove noise from the output signal based on a timing control signal. The timing control signal is activated during a first comparison duration, in which a first comparison operation is performed with respect to the ramp signal and the reset component of the input signal, and during a second comparison duration, in which a second comparison operation is performed with respect to the ramp signal and the image component of the input signal.

Abstract translation: 包括在图像传感器中的相关双采样（CDS）电路包括采样单元和定时控制带限（TCBL）单元。 采样单元被配置为通过基于斜坡信号对输入信号的复位分量和输入信号的图像分量执行CDS操作来产生输出信号，该输入信号从包括在 图像传感器。 TCBL单元连接到采样单元，并且被配置为基于定时控制信号从输出信号中去除噪声。 定时控制信号在第一比较持续时间期间被激活，其中相对于斜坡信号和输入信号的复位分量执行第一比较操作，并且在执行第二比较操作的第二比较持续时间期间 相对于斜坡信号和输入信号的图像分量。

公开(公告)号：US09521345B2

公开(公告)日：2016-12-13

申请号：US14559854

申请日：2014-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Young Jin ,  Hyuk-Bin Kwon ,  Dae-Hwa Paik ,  Chang-Eun Kang ,  Won-Ho Choi ,  Young-Tae Jang ,  Ji-Hun Shin ,  Young-Kyun Jeong

IPC: H04N5/378 ,  H04N5/376

CPC classification number: H04N5/378 ,  H04N5/3765

Abstract: A data transmission circuit includes a data output unit (DOU) connected to a positive data transmission line and a negative data transmission line. The DOU generates a recovered data signal based on data signals communicated via the positive and negative data transmission lines. Data signal driving units are respectively connected at different points along the positive and negative data transmission lines, where each data signal driving unit generates and provides a positive data signal and a negative data signal based on a data input signal and a data transmission distance between the data signal driving unit and the data output unit.

Abstract translation: 数据传输电路包括连接到正数据传输线和负数据传输线的数据输出单元（DOU）。 DOU根据通过正和负数据传输线传送的数据信号产生恢复的数据信号。 数据信号驱动单元分别连接在正负数据传输线的不同点，其​​中每个数据信号驱动单元基于数据输入信号产生正数据信号和负数据信号，并且提供数据信号驱动单元之间的数据传输距离 数据信号驱动单元和数据输出单元。

公开(公告)号：US09258506B2

公开(公告)日：2016-02-09

申请号：US14335309

申请日：2014-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hun Shin ,  Chang-Eun Kang ,  Won-Ho Choi ,  Dong-Hun Lee

IPC: H04N5/335 ,  H04N5/378 ,  H03K21/38 ,  H03K23/66 ,  H03M1/14 ,  H03M1/12 ,  H03M1/56 ,  H04N5/357 ,  H04N5/369 ,  H04N5/3745 ,  H04N13/02

CPC classification number: H04N5/378 ,  H03K21/38 ,  H03K23/667 ,  H03M1/123 ,  H03M1/14 ,  H03M1/56 ,  H04N5/3575 ,  H04N5/3696 ,  H04N5/3745 ,  H04N13/243 ,  H04N13/254 ,  H04N13/271 ,  H04N2213/001

Abstract: A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (N−M)-bit signals of N-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval. N and M are natural numbers, N is greater than M, and M is greater than or equal to 3. The second counter is configured to count a second counter clock signal which toggles with a second frequency which is higher than the first frequency to generate lower M-bit signals of the N-bit counter output signals, in response to a second counting enable signal based on the first comparison signal and a second comparison signal during a fine counting interval which follows the coarse counting interval.

Abstract translation: 计数器电路包括第一计数器和第二计数器。 第一计数器被配置为响应于基于第一比较的第一计数使能信号来计数与第一频率切换的第一计数器时钟信号，以产生N位计数器输出信号的上（N-M）位信号 信号在粗计数间隔期间。 N和M是自然数，N大于M，M大于或等于3.第二计数器被配置为对第二计数器时钟信号进行计数，第二计数器时钟信号与第二频率相交换，第二频率高于第一频率以产生 响应于基于第一比较信号的第二计数使能信号和在粗计数间隔之后的精细计数间隔期间的第二比较信号，N比特计数器输出信号的较低M比特信号。