Method of binning pixels in an image sensor and an image sensor for performing the same
    1.
    发明授权
    Method of binning pixels in an image sensor and an image sensor for performing the same 有权
    对图像传感器中的像素进行合并的方法和用于执行图像传感器的图像传感器

    公开(公告)号:US09584742B2

    公开(公告)日:2017-02-28

    申请号:US14540450

    申请日:2014-11-13

    CPC classification number: H04N5/347

    Abstract: A method of binning pixels in an image sensor including: dividing a pixel array into a plurality of binning areas, wherein each binning area includes (2n)*(2n) pixels, wherein n is an integer equal to or greater than two; and generating binning pixel data in each of the binning areas, wherein the locations of the binning pixel data of each binning area are evenly distributed within the binning area.

    Abstract translation: 一种对图像传感器中的像素进行合并的方法,包括:将像素阵列划分成多个合并区域,其中每个合并区域包括(2n)*(2n)个像素,其中n是等于或大于2的整数; 以及在每个合并区域中生成合并像素数据,其中每个合并区域的合并像素数据的位置均匀分布在合并区域内。

    Digital double sampling method, a related CMOS image sensor, and a digital camera comprising the CMOS image sensor
    2.
    发明授权
    Digital double sampling method, a related CMOS image sensor, and a digital camera comprising the CMOS image sensor 有权
    数字双采样方法,相关的CMOS图像传感器和包括CMOS图像传感器的数字照相机

    公开(公告)号:US09538105B2

    公开(公告)日:2017-01-03

    申请号:US14934718

    申请日:2015-11-06

    Abstract: A digital double sampling method, a related complementary metal oxide semiconductor (CMOS) image sensor, and a digital camera comprising the CMOS image sensor are disclosed. The method includes generating first digital data corresponding to an initial voltage level apparent in a pixel in response to a reset signal, inverting the first digital data, outputting a detection voltage corresponding to image data received from outside of the CMOS image sensor, and counting in synchronization with a clock signal, starting from an initial value equal to the inverted first digital data, and for an amount of time responsive to a voltage level of the detection voltage.

    Abstract translation: 公开了一种数字双采样方法,相关的互补金属氧化物半导体(CMOS)图像传感器和包括CMOS图像传感器的数字照相机。 该方法包括响应于复位信号产生对应于像素中显而易见的初始电压电平的第一数字数据,反转第一数字数据,输出对应于从CMOS图像传感器外部接收的图像数据的检测电压,并计数 与等于反相的第一数字数据的初始值开始的时钟信号的同步,以及响应于检测电压的电压电平的时间量。

    Image sensor and computing system having the same
    3.
    发明授权
    Image sensor and computing system having the same 有权
    图像传感器和计算系统具有相同的功能

    公开(公告)号:US09344627B2

    公开(公告)日:2016-05-17

    申请号:US14105594

    申请日:2013-12-13

    CPC classification number: H04N5/23245 H04N5/378

    Abstract: An image sensor includes a pixel array and an analog-to-digital (A/D) conversion unit. The pixel array generates an analog signal by sensing an incident light. The A/D conversion unit generates a digital signal in a first operation mode by performing a sigma-delta A/D conversion and a cyclic A/D conversion with respect to the analog signal and generates the digital signal in a second operation mode by performing a single-slope A/D conversion with respect to the analog signal. The image sensor provides a high-quality image in a still image photography mode and a dynamic image video mode.

    Abstract translation: 图像传感器包括像素阵列和模数(A / D)转换单元。 像素阵列通过感测入射光产生模拟信号。 A / D转换单元通过对模拟信号执行Σ-ΔA/ D转换和循环A / D转换,以第一操作模式产生数字信号,并通过执行第二操作模式生成数字信号 相对于模拟信号的单斜率A / D转换。 图像传感器在静态图像拍摄模式和动态图像视频模式中提供高质量的图像。

    Unit pixels configured to output different pixel signals through different lines and image sensors including the same
    5.
    发明授权
    Unit pixels configured to output different pixel signals through different lines and image sensors including the same 有权
    单位像素被配置为通过不同的线和图像传感器输出不同的像素信号,包括它们

    公开(公告)号:US09232161B2

    公开(公告)日:2016-01-05

    申请号:US14206126

    申请日:2014-03-12

    CPC classification number: H04N5/3575 H04N5/37457 H04N5/378 H04N9/045

    Abstract: An image sensor includes a pixel array and a plurality of pairs of column lines. The pixel array includes a plurality of unit pixel areas arranged in a plurality of rows and columns. Each of the unit pixel areas includes a readout circuit connected to a corresponding pair of column lines, and first and second photo-electric conversion devices sharing the readout circuit. Each of the unit pixel areas is configured to output a first pixel signal corresponding to a photoelectron generated by the first photo-electric conversion device through the first column line, and to output a second pixel signal corresponding to a photoelectron generated by the second photo-electric conversion device through the second column line.

    Abstract translation: 图像传感器包括像素阵列和多对列线。 像素阵列包括以多个行和列排列的多个单位像素区域。 每个单位像素区域包括连接到相应的一对列线的读出电路,以及共享读出电路的第一和第二光电转换装置。 每个单位像素区域被配置为通过第一列线输出与由第一光电转换装置产生的光电子相对应的第一像素信号,并且输出与由第二光电转换装置产生的光电子相对应的第二像素信号, 电转换装置通过第二列线。

    Correlated double sampling circuit and image sensor including the same
    6.
    发明授权
    Correlated double sampling circuit and image sensor including the same 有权
    相关的双采样电路和图像传感器包括相同的

    公开(公告)号:US09191599B2

    公开(公告)日:2015-11-17

    申请号:US13778591

    申请日:2013-02-27

    CPC classification number: H04N5/378 H04N5/3575

    Abstract: A correlated double sampling (CDS) circuit included in an image sensor includes a sampling unit and a timing controlled band-limitation (TCBL) unit. The sampling unit is configured to generate an output signal by performing a CDS operation with respect to a reset component of an input signal and an image component of the input signal based on a ramp signal, the input signal being provided from a pixel array included in the image sensor. The TCBL unit is connected to the sampling unit, and is configured to remove noise from the output signal based on a timing control signal. The timing control signal is activated during a first comparison duration, in which a first comparison operation is performed with respect to the ramp signal and the reset component of the input signal, and during a second comparison duration, in which a second comparison operation is performed with respect to the ramp signal and the image component of the input signal.

    Abstract translation: 包括在图像传感器中的相关双采样(CDS)电路包括采样单元和定时控制带限(TCBL)单元。 采样单元被配置为通过基于斜坡信号对输入信号的复位分量和输入信号的图像分量执行CDS操作来产生输出信号,该输入信号从包括在 图像传感器。 TCBL单元连接到采样单元,并且被配置为基于定时控制信号从输出信号中去除噪声。 定时控制信号在第一比较持续时间期间被激活,其中相对于斜坡信号和输入信号的复位分量执行第一比较操作,并且在执行第二比较操作的第二比较持续时间期间 相对于斜坡信号和输入信号的图像分量。

    IMAGE SENSOR AND COMPUTING SYSTEM HAVING THE SAME
    7.
    发明申请
    IMAGE SENSOR AND COMPUTING SYSTEM HAVING THE SAME 有权
    图像传感器和计算机系统

    公开(公告)号:US20140232890A1

    公开(公告)日:2014-08-21

    申请号:US14105594

    申请日:2013-12-13

    CPC classification number: H04N5/23245 H04N5/378

    Abstract: An image sensor includes a pixel array and an analog-to-digital (A/D) conversion unit. The pixel array generates an analog signal by sensing an incident light. The A/D conversion unit generates a digital signal in a first operation mode by performing a sigma-delta A/D conversion and a cyclic A/D conversion with respect to the analog signal and generates the digital signal in a second operation mode by performing a single-slope A/D conversion with respect to the analog signal. The image sensor provides a high-quality image in a still image photography mode and a dynamic image video mode.

    Abstract translation: 图像传感器包括像素阵列和模数(A / D)转换单元。 像素阵列通过感测入射光产生模拟信号。 A / D转换单元通过对模拟信号执行Σ-ΔA/ D转换和循环A / D转换,以第一操作模式产生数字信号,并通过执行第二操作模式生成数字信号 相对于模拟信号的单斜率A / D转换。 图像传感器在静态图像拍摄模式和动态图像视频模式中提供高质量的图像。

    Line memory device and image sensor including the same
    9.
    发明授权
    Line memory device and image sensor including the same 有权
    线路存储器件和包括其的图像传感器

    公开(公告)号:US09135963B2

    公开(公告)日:2015-09-15

    申请号:US13757977

    申请日:2013-02-04

    Abstract: A line memory device includes a plurality of memory cells, a data line pair, a sense amplifier and an output unit. The plurality of memory cells are disposed adjacent to each other in a line. The data line pair is coupled to the memory cells to sequentially transfer memory data bits stored in the memory cells to the sense amplifier. The sense amplifier is configured to amplify the memory data bits that are sequentially transferred through the data line pair by corresponding delay times which are different from each other. The output unit samples an output of the sense amplifier to sequentially output retimed data bits of the memory data bits in response to a read clock signal. The read clock signal has a cyclic period which is less than a maximum delay time among the delay times.

    Abstract translation: 行存储器件包括多个存储单元,数据线对,读出放大器和输出单元。 多个存储单元被一行地相邻配置。 数据线对耦合到存储器单元以将存储在存储器单元中的存储器数据位顺序传送到读出放大器。 读出放大器被配置为放大通过数据线对顺序传送的存储器数据位,相应的延迟时间彼此不同。 输出单元对读出放大器的输出进行采样,以响应读取的时钟信号顺序地输出存储器数据位的重新定时数据位。 读取时钟信号具有小于延迟时间之间的最大延迟时间的循环周期。

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