Abstract:
A method of binning pixels in an image sensor including: dividing a pixel array into a plurality of binning areas, wherein each binning area includes (2n)*(2n) pixels, wherein n is an integer equal to or greater than two; and generating binning pixel data in each of the binning areas, wherein the locations of the binning pixel data of each binning area are evenly distributed within the binning area.
Abstract:
A digital double sampling method, a related complementary metal oxide semiconductor (CMOS) image sensor, and a digital camera comprising the CMOS image sensor are disclosed. The method includes generating first digital data corresponding to an initial voltage level apparent in a pixel in response to a reset signal, inverting the first digital data, outputting a detection voltage corresponding to image data received from outside of the CMOS image sensor, and counting in synchronization with a clock signal, starting from an initial value equal to the inverted first digital data, and for an amount of time responsive to a voltage level of the detection voltage.
Abstract:
An image sensor includes a pixel array and an analog-to-digital (A/D) conversion unit. The pixel array generates an analog signal by sensing an incident light. The A/D conversion unit generates a digital signal in a first operation mode by performing a sigma-delta A/D conversion and a cyclic A/D conversion with respect to the analog signal and generates the digital signal in a second operation mode by performing a single-slope A/D conversion with respect to the analog signal. The image sensor provides a high-quality image in a still image photography mode and a dynamic image video mode.
Abstract:
A digital double sampling method, a related complementary metal oxide semiconductor (CMOS) image sensor, and a digital camera comprising the CMOS image sensor are disclosed. The method includes generating first digital data corresponding to an initial voltage level apparent in a pixel in response to a reset signal, inverting the first digital data, outputting a detection voltage corresponding to image data received from outside of the CMOS image sensor, and counting in synchronization with a clock signal, starting from an initial value equal to the inverted first digital data, and for an amount of time responsive to a voltage level of the detection voltage.
Abstract:
An image sensor includes a pixel array and a plurality of pairs of column lines. The pixel array includes a plurality of unit pixel areas arranged in a plurality of rows and columns. Each of the unit pixel areas includes a readout circuit connected to a corresponding pair of column lines, and first and second photo-electric conversion devices sharing the readout circuit. Each of the unit pixel areas is configured to output a first pixel signal corresponding to a photoelectron generated by the first photo-electric conversion device through the first column line, and to output a second pixel signal corresponding to a photoelectron generated by the second photo-electric conversion device through the second column line.
Abstract:
A correlated double sampling (CDS) circuit included in an image sensor includes a sampling unit and a timing controlled band-limitation (TCBL) unit. The sampling unit is configured to generate an output signal by performing a CDS operation with respect to a reset component of an input signal and an image component of the input signal based on a ramp signal, the input signal being provided from a pixel array included in the image sensor. The TCBL unit is connected to the sampling unit, and is configured to remove noise from the output signal based on a timing control signal. The timing control signal is activated during a first comparison duration, in which a first comparison operation is performed with respect to the ramp signal and the reset component of the input signal, and during a second comparison duration, in which a second comparison operation is performed with respect to the ramp signal and the image component of the input signal.
Abstract:
An image sensor includes a pixel array and an analog-to-digital (A/D) conversion unit. The pixel array generates an analog signal by sensing an incident light. The A/D conversion unit generates a digital signal in a first operation mode by performing a sigma-delta A/D conversion and a cyclic A/D conversion with respect to the analog signal and generates the digital signal in a second operation mode by performing a single-slope A/D conversion with respect to the analog signal. The image sensor provides a high-quality image in a still image photography mode and a dynamic image video mode.
Abstract:
A line memory device includes a plurality of memory cells, a data line pair, a sense amplifier and an output unit. The plurality of memory cells are disposed adjacent to each other in a line. The data line pair is coupled to the memory cells to sequentially transfer memory data bits stored in the memory cells to the sense amplifier. The sense amplifier is configured to amplify the memory data bits that are sequentially transferred through the data line pair by corresponding delay times which are different from each other. The output unit samples an output of the sense amplifier to sequentially output retimed data bits of the memory data bits in response to a read clock signal. The read clock signal has a cyclic period which is less than a maximum delay time among the delay times.
Abstract:
A line memory device includes a plurality of memory cells, a data line pair, a sense amplifier and an output unit. The plurality of memory cells are disposed adjacent to each other in a line. The data line pair is coupled to the memory cells to sequentially transfer memory data bits stored in the memory cells to the sense amplifier. The sense amplifier is configured to amplify the memory data bits that are sequentially transferred through the data line pair by corresponding delay times which are different from each other. The output unit samples an output of the sense amplifier to sequentially output retimed data bits of the memory data bits in response to a read clock signal. The read clock signal has a cyclic period which is less than a maximum delay time among the delay times.