公开(公告)号：US20240074154A1

公开(公告)日：2024-02-29

申请号：US18126395

申请日：2023-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonhaeng LEE ,  SANGWOO PAE ,  NAMHYUN LEE

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/50

Abstract: A semiconductor memory may include a substrate, a buried dielectric layer on the substrate and providing a first recess that extends in a first direction, a word line in the first recess of the buried dielectric layer, first and second source/drain patterns on opposite sides of the word line, a channel pattern between the word line and the first recess of the buried dielectric layer and contacting the first and second source/drain patterns, and a bit line electrically connected to the second source/drain pattern and extending in a second direction that intersects the first direction. The channel pattern includes vertical parts and a horizontal part connected to each other. The vertical parts are on opposite lateral surfaces of the word line. The horizontal part is below the word line.

公开(公告)号：US20240047339A1

公开(公告)日：2024-02-08

申请号：US18106540

申请日：2023-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGMIN CHA ,  SEUNGMIN SONG ,  YOUNGWOO KIM ,  JINKYU KIM ,  SORA YOU ,  NAMHYUN LEE ,  SUNGMOON LEE

IPC: H01L23/50 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L23/535 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/50 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/66545 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/4236 ,  H01L23/535 ,  H01L23/5226 ,  H01L23/5286

Abstract: An integrated circuit device includes a substrate, having a front surface and a rear surface opposite to each other, and a fin-type active region defined by a trench in the front surface, a device separation layer filling the trench, a source/drain region on the fin-type active region, a first conductive plug arranged on the source/drain region and electrically connected to the source/drain region, a power wiring line at least partially arranged on a lower surface of the substrate, a buried rail connected to the power wiring line through the device separation layer and decreasing in horizontal width toward the power wiring line, and a power via connecting the buried rail to the first conductive plug.