公开(公告)号：US20240074154A1

公开(公告)日：2024-02-29

申请号：US18126395

申请日：2023-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonhaeng LEE ,  SANGWOO PAE ,  NAMHYUN LEE

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/50

Abstract: A semiconductor memory may include a substrate, a buried dielectric layer on the substrate and providing a first recess that extends in a first direction, a word line in the first recess of the buried dielectric layer, first and second source/drain patterns on opposite sides of the word line, a channel pattern between the word line and the first recess of the buried dielectric layer and contacting the first and second source/drain patterns, and a bit line electrically connected to the second source/drain pattern and extending in a second direction that intersects the first direction. The channel pattern includes vertical parts and a horizontal part connected to each other. The vertical parts are on opposite lateral surfaces of the word line. The horizontal part is below the word line.

公开(公告)号：US20240347631A1

公开(公告)日：2024-10-17

申请号：US18509483

申请日：2023-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonhaeng LEE ,  DONGHEE SON

IPC: H01L29/78 ,  H10B12/00

CPC classification number: H01L29/7831 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488

Abstract: A semiconductor device includes an outer active pattern on a substrate, the outer active pattern having a trench crossing the outer active pattern, an outer word line covering a wall of the trench, an inner active pattern covering the outer word line in the trench, an inner word line covering the inner active pattern in the trench, and a separation insulating pattern interposed between the outer word line and the inner active pattern in the trench. The outer word line and the inner word line are insulated from each other.

公开(公告)号：US20230164978A1

公开(公告)日：2023-05-25

申请号：US17882215

申请日：2022-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonhaeng LEE ,  Iloh JANG ,  Jisook HONG

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/1085 ,  H01L27/10888

Abstract: The present disclosure refers to memory devices and manufacturing methods thereof. In an embodiment, a memory device includes a memory cell array, a first dummy capacitor, a second dummy capacitor, and a third dummy capacitor. The memory cell array includes gate structures formed on a substrate, first active regions adjacent to the gate structures, gate insulating layers disposed between the gate structures and the first active regions, and cell capacitors connected to the first active regions. The first and second dummy capacitors extend in a first direction and in the vertical direction, and are disposed to be adjacent to the memory cell array in a second direction. The third dummy capacitor extends in the second direction and the vertical direction and is disposed to be adjacent to the memory cell array in the first direction. The memory cell array is disposed between the first and second dummy capacitors.

公开(公告)号：US20240258203A1

公开(公告)日：2024-08-01

申请号：US18459588

申请日：2023-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonhaeng LEE ,  Hyunggyun NOH ,  Sung-Mock HA

IPC: H01L23/48 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/0657 ,  H01L2225/06544

Abstract: A semiconductor device may include a substrate having a first surface and a second surface opposite to the first surface, a protection layer on the first surface of the substrate, metal layers in the substrate, extending in a first direction parallel to the first surface, and spaced apart from each other in a second direction perpendicular to the first surface, a via structure vertically penetrating the metal layers and the substrate, a circuit layer on the second surface of the substrate, and a connection terminal on a bottom surface of the circuit layer. Each of the metal layers may have a tetragonal or circular shape, when viewed in a plan view.

公开(公告)号：US20240047579A1

公开(公告)日：2024-02-08

申请号：US18199504

申请日：2023-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonhaeng LEE

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/22 ,  H01L21/762 ,  H10B12/00 ,  H10B41/00 ,  H10B43/00

CPC classification number: H01L29/7833 ,  H01L21/76898 ,  H01L21/22 ,  H01L21/762 ,  H01L21/76832 ,  H10B12/30 ,  H10B41/00 ,  H10B43/00

Abstract: A semiconductor device includes a substrate including first and second surfaces opposing each other. A device isolation layer extends through the substrate and defines an active region in the substrate. A gate electrode is on the first surface of the substrate. A wiring structure electrically connects the gate electrode and the active region. The active region includes a target doped region between the device isolation layer and the gate electrode and including a dopant having a first concentration. A path doped region is between the device isolation layer and the gate electrode and extends from the second surface of the substrate to the target doped region. The path doped region includes a dopant having a second concentration less than the first concentration. The target doped region and the path doped region are formed by implanting the dopant through the second surface of the substrate.