公开(公告)号：US20220253682A1

公开(公告)日：2022-08-11

申请号：US17375197

申请日：2021-07-14

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Seung Wook LEE ,  Jaeyeon WON ,  Jae Wook LEE ,  Tae Jun HAM

IPC: G06N3/063 ,  G06F7/544 ,  G06F7/523 ,  G06F7/50 ,  G06F7/76 ,  G06F5/01

Abstract: A processor, a method of operating the processor, and an electronic device including the processor are disclosed. The method includes arranging, in respective input registers, weights and activations having a smaller number of bits than a minimum operation unit of an operator included in the processor, performing a multiplication between values stored in the input registers, storing a result of the multiplication in an output register, and outputting, from the output register, a value in a preset bit range as a result of a dot product between a first vector including the weights and a second vector including the activations.

公开(公告)号：US20220225506A1

公开(公告)日：2022-07-14

申请号：US17375307

申请日：2021-07-14

Applicant: Samsung Electronics Co., Ltd. ,  SNU R&DB Foundation

Inventor： Seung Wook LEE ,  Jangwoo KIM ,  Pyeongsu PARK

IPC: H05K1/14 ,  H05K1/02 ,  G06F9/50 ,  G06F9/54

Abstract: An electronic device includes: a host box comprising a host processor configured to control an operation of the electronic device, a host motherboard in which the host processor is disposed, and a host power supply unit (PSU) configured to supply power to a component connected to the host motherboard; and one or more extension boxes controlled by the host box, wherein each of the one or more extension boxes comprises an extension motherboard independent of the host box, and an extension PSU independent of the host box and configured to supply power to a component connected to the extension motherboard.

公开(公告)号：US20220083390A1

公开(公告)日：2022-03-17

申请号：US17223139

申请日：2021-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Jae-Eon JO ,  Hyung-Dal KWON ,  Hanmin PARK ,  Jaehyeong SIM ,  Seung Wook LEE

IPC: G06F9/50 ,  G06N3/04 ,  G06N3/063 ,  G06F9/48 ,  G06F1/3237

Abstract: A computing device and method is disclosed. The computing device includes a plurality of processing cores, and a tile scheduler configured to update a cost matrix of each of the plurality of processing cores based on meta information of each of first tiles previously allocated to the plurality of processing cores and meta information of each of second tiles, and allocate the second tiles with respect to the plurality of processing cores using the updated cost matrix of each of the plurality of processing cores.

公开(公告)号：US20210263870A1

公开(公告)日：2021-08-26

申请号：US17143539

申请日：2021-01-07

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SNU R&DB Foundation

Inventor： Seung Wook LEE ,  Jung Ho AHN ,  Hweesoo KIM

IPC: G06F13/28 ,  G06N3/063

Abstract: An accelerator, an operation method of the accelerator, and an accelerator apparatus including the accelerator are disclosed. The operation method includes receiving one or more workloads assigned by a main processor, performing at least one operation involved with the workloads in an internal memory of the accelerator or in a direct memory access (DMA) configured to control data input to or output from the internal memory, and providing a result of performing the at least one operation.

公开(公告)号：US20220164164A1

公开(公告)日：2022-05-26

申请号：US17356771

申请日：2021-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung-Dal KWON ,  Ho Young KIM ,  Hanmin PARK ,  Jaehyeong SIM ,  Seung Wook LEE ,  Jae-Eon JO

IPC: G06F7/50 ,  G06N3/08 ,  G06F7/544

Abstract: An apparatus with deep learning includes: a systolic adder tree including adder trees connected in row and column directions; and an input multiplexer connected to an input register of at least one of the adder trees and configured to determine column directional data movement between the adder trees based on operation modes.

公开(公告)号：US20220114015A1

公开(公告)日：2022-04-14

申请号：US17195748

申请日：2021-03-09

Applicant: Samsung Electronics Co., Ltd ,  SNU R&DB FOUNDATION

Inventor： Seung Wook LEE ,  Younghwan OH ,  Jaewook LEE ,  Sam SON ,  Yunho JIN ,  Taejun HAM

IPC: G06F9/48 ,  G06N5/04

Abstract: A scheduler, a method of operating the scheduler, and an electronic device including the scheduler are disclosed. The method of operating the scheduler configured to determine a model to be executed in an accelerator includes receiving one or more requests for execution of a plurality of models to be independently executed in the accelerator, and performing layer-wise scheduling on the models based on an idle time occurring when a candidate layer which is a target for the scheduling in each of the models is executed in the accelerator

公开(公告)号：US20210397557A1

公开(公告)日：2021-12-23

申请号：US17148676

申请日：2021-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Seoul National University R&DB Foundation

Inventor： Jaejin LEE ,  Heehoon KIM ,  Seung Wook LEE

IPC: G06F12/0862 ,  G06N3/08 ,  G06F12/0842

Abstract: An accelerator includes processing elements configured to perform an operation associated with an instruction received from a host processor, hierarchical memories configured to be accessible by any one or any combination of any two or more of the processing elements, and sub-cores configured to prefetch data associated with the operation to a memory of a corresponding level of the hierarchical memories.

公开(公告)号：US20210263865A1

公开(公告)日：2021-08-26

申请号：US17165018

申请日：2021-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SNU R&DB FOUNDATION

Inventor： Seung Wook LEE ,  Soojung RYU ,  Jintaek KANG ,  Sunjung LEE

IPC: G06F13/16 ,  G06N3/04 ,  G06N3/10 ,  G06F13/28 ,  G06F7/544

Abstract: An accelerator, an operation method of the accelerator, and an accelerator system including the accelerator are disclosed. The operation method includes receiving one or more workloads assigned by a host controller, determining reuse data of the workloads based on hardware resource information and/or a memory access cost of the accelerator when a plurality of processing units included in the accelerator performs the workloads, and providing a result of performing the workloads.

公开(公告)号：US20230342311A1

公开(公告)日：2023-10-26

申请号：US18212979

申请日：2023-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  SNU R&DB FOUNDATION

Inventor： Seung Wook LEE ,  Soojung RYU ,  Jintaek KANG ,  Sunjung LEE

IPC: G06F13/16 ,  G06F7/544 ,  G06F13/28 ,  G06N3/04 ,  G06N3/10

CPC classification number: G06F13/1668 ,  G06F7/5443 ,  G06F13/28 ,  G06N3/04 ,  G06N3/10

Abstract: An accelerator, an operation method of the accelerator, and an accelerator system including the accelerator are disclosed. The operation method includes receiving one or more workloads assigned on an accelerator, determining reuse data of the workloads based on hardware resource information and/or a memory access cost of the accelerator when a plurality of processing units included in the accelerator performs the workloads, and providing a result of performing the workloads.

公开(公告)号：US20220283851A1

公开(公告)日：2022-09-08

申请号：US17402848

申请日：2021-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Seoul National University R&DB Foundation

Inventor： Seung Wook LEE ,  Jangwoo KIM ,  Pyeongsu PARK

IPC: G06F9/48 ,  G06F9/54

Abstract: An electronic device includes: a host processor configured to control an operation of the electronic device; accelerators of heterogeneous hardware types configured to exchange data with each other through direct communication; and a control unit configured to convert a command received from the host processor, based on a type of each of the accelerators and transfer a result of the converting to a corresponding accelerator among the accelerators.