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公开(公告)号：US20220225506A1
公开(公告)日：2022-07-14
申请号：US17375307
申请日：2021-07-14
发明人： Seung Wook LEE , Jangwoo KIM , Pyeongsu PARK
摘要： An electronic device includes: a host box comprising a host processor configured to control an operation of the electronic device, a host motherboard in which the host processor is disposed, and a host power supply unit (PSU) configured to supply power to a component connected to the host motherboard; and one or more extension boxes controlled by the host box, wherein each of the one or more extension boxes comprises an extension motherboard independent of the host box, and an extension PSU independent of the host box and configured to supply power to a component connected to the extension motherboard.
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2.发明申请公开(公告)号：US20210263870A1
公开(公告)日：2021-08-26
申请号：US17143539
申请日：2021-01-07
发明人： Seung Wook LEE , Jung Ho AHN , Hweesoo KIM
摘要： An accelerator, an operation method of the accelerator, and an accelerator apparatus including the accelerator are disclosed. The operation method includes receiving one or more workloads assigned by a main processor, performing at least one operation involved with the workloads in an internal memory of the accelerator or in a direct memory access (DMA) configured to control data input to or output from the internal memory, and providing a result of performing the at least one operation.
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公开(公告)号：US20220114015A1
公开(公告)日：2022-04-14
申请号：US17195748
申请日：2021-03-09
发明人： Seung Wook LEE , Younghwan OH , Jaewook LEE , Sam SON , Yunho JIN , Taejun HAM
摘要： A scheduler, a method of operating the scheduler, and an electronic device including the scheduler are disclosed. The method of operating the scheduler configured to determine a model to be executed in an accelerator includes receiving one or more requests for execution of a plurality of models to be independently executed in the accelerator, and performing layer-wise scheduling on the models based on an idle time occurring when a candidate layer which is a target for the scheduling in each of the models is executed in the accelerator
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公开(公告)号：US20210263865A1
公开(公告)日：2021-08-26
申请号：US17165018
申请日：2021-02-02
发明人： Seung Wook LEE , Soojung RYU , Jintaek KANG , Sunjung LEE
摘要： An accelerator, an operation method of the accelerator, and an accelerator system including the accelerator are disclosed. The operation method includes receiving one or more workloads assigned by a host controller, determining reuse data of the workloads based on hardware resource information and/or a memory access cost of the accelerator when a plurality of processing units included in the accelerator performs the workloads, and providing a result of performing the workloads.
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公开(公告)号：US20230342311A1
公开(公告)日：2023-10-26
申请号：US18212979
申请日：2023-06-22
发明人： Seung Wook LEE , Soojung RYU , Jintaek KANG , Sunjung LEE
CPC分类号： G06F13/1668 , G06F7/5443 , G06F13/28 , G06N3/04 , G06N3/10
摘要： An accelerator, an operation method of the accelerator, and an accelerator system including the accelerator are disclosed. The operation method includes receiving one or more workloads assigned on an accelerator, determining reuse data of the workloads based on hardware resource information and/or a memory access cost of the accelerator when a plurality of processing units included in the accelerator performs the workloads, and providing a result of performing the workloads.
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公开(公告)号：US20220365891A1
公开(公告)日：2022-11-17
申请号：US17876116
申请日：2022-07-28
发明人： Seung Wook LEE , Hweesoo KIM , Jung Ho AHN
摘要： An accelerator includes: a memory configured to store input data; a plurality of shift buffers each configured to shift input data received sequentially from the memory in each cycle, and in response to input data being stored in each of internal elements of the shift buffer, output the stored input data to a processing element (PE) array; a plurality of backup buffers each configured to store input data received sequentially from the memory and transfer the stored input data to one of the shift buffers; and the PE array configured to perform an operation on input data received from one or more of the shift buffers and on a corresponding kernel.
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公开(公告)号：US20220114116A1
公开(公告)日：2022-04-14
申请号：US17192032
申请日：2021-03-04
发明人： Seung Wook LEE , Hweesoo KIM , Jung Ho AHN
摘要： An accelerator includes: a memory configured to store input data; a plurality of shift buffers each configured to shift input data received sequentially from the memory in each cycle, and in response to input data being stored in each of internal elements of the shift buffer, output the stored input data to a processing element (PE) array; a plurality of backup buffers each configured to store input data received sequentially from the memory and transfer the stored input data to one of the shift buffers; and the PE array configured to perform an operation on input data received from one or more of the shift buffers and on a corresponding kernel.
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公开(公告)号：US20220253682A1
公开(公告)日：2022-08-11
申请号：US17375197
申请日：2021-07-14
发明人： Seung Wook LEE , Jaeyeon WON , Jae Wook LEE , Tae Jun HAM
摘要： A processor, a method of operating the processor, and an electronic device including the processor are disclosed. The method includes arranging, in respective input registers, weights and activations having a smaller number of bits than a minimum operation unit of an operator included in the processor, performing a multiplication between values stored in the input registers, storing a result of the multiplication in an output register, and outputting, from the output register, a value in a preset bit range as a result of a dot product between a first vector including the weights and a second vector including the activations.
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公开(公告)号：US20220083390A1
公开(公告)日：2022-03-17
申请号：US17223139
申请日：2021-04-06
发明人： Jae-Eon JO , Hyung-Dal KWON , Hanmin PARK , Jaehyeong SIM , Seung Wook LEE
IPC分类号： G06F9/50 , G06N3/04 , G06N3/063 , G06F9/48 , G06F1/3237
摘要： A computing device and method is disclosed. The computing device includes a plurality of processing cores, and a tile scheduler configured to update a cost matrix of each of the plurality of processing cores based on meta information of each of first tiles previously allocated to the plurality of processing cores and meta information of each of second tiles, and allocate the second tiles with respect to the plurality of processing cores using the updated cost matrix of each of the plurality of processing cores.
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公开(公告)号：US20220164164A1
公开(公告)日：2022-05-26
申请号：US17356771
申请日：2021-06-24
发明人： Hyung-Dal KWON , Ho Young KIM , Hanmin PARK , Jaehyeong SIM , Seung Wook LEE , Jae-Eon JO
摘要： An apparatus with deep learning includes: a systolic adder tree including adder trees connected in row and column directions; and an input multiplexer connected to an input register of at least one of the adder trees and configured to determine column directional data movement between the adder trees based on operation modes.
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