公开(公告)号：US20250015043A1

公开(公告)日：2025-01-09

申请号：US18748295

申请日：2024-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeean LEE ,  Dongwon KANG ,  Changyeon SONG ,  Sunguk LEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes: a first redistribution structure including a first upper connection pad and a first lower connection pad; a first semiconductor device on the first redistribution structure; a vertical connection conductor on the first redistribution structure; an encapsulant adjacent to the first semiconductor device; a second redistribution structure on the encapsulant and including a second redistribution pattern, a second insulating layer, a second upper connection pad, and a second lower connection pad; an insulating adhesive layer between the second redistribution structure and the encapsulant; and an intermediate connection terminal connecting the second lower connection pad with the vertical connection conductor, wherein the second upper connection pad is exposed by an upper opening of the second insulating layer. A cover conductive layer is on the second upper connection pad. A side surface of the intermediate connection terminal is covered with the insulating adhesive layer and the encapsulant.

公开(公告)号：US20220238469A1

公开(公告)日：2022-07-28

申请号：US17718639

申请日：2022-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngkyu LIM ,  Gookmi SONG ,  Sunguk LEE

IPC: H01L23/00

Abstract: A package substrate may include an insulation substrate, at least one redistribution layer (RDL) and a redistribution pad. The RDL may be included in the insulation substrate. The redistribution pad may extend from the RDL. The redistribution pad may include at least one segmenting groove in a radial direction of the redistribution pad. Thus, the at least one segmenting groove in the radial direction of the redistribution pad may reduce an area of the redistribution pad. Therefore, application of physical stress to a PID disposed over the redistribution pad may be suppressed, and thus generation of cracks in the PID may be reduced. Further, spreading of the cracks toward the redistribution pad from the PID may also be suppressed, and thus reliability the semiconductor package may be improved.

公开(公告)号：US20250046728A1

公开(公告)日：2025-02-06

申请号：US18429538

申请日：2024-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongwon KANG ,  Hongwon KIM ,  Changyeon SONG ,  Sunguk LEE ,  Jae-Ean LEE

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package may include a semiconductor chip and an upper redistribution layer including a marking structure on the semiconductor chip, an upper insulating layer surrounding the marking structure, and an outer insulating layer on the upper insulating layer, wherein the marking structure may include a lower marking pattern, a marking via on the lower marking pattern, and an upper marking pattern on the marking via, the upper marking pattern may include a first conductive pattern on the marking via and a second conductive pattern on the first conductive pattern, and the second conductive pattern may be exposed by a trench defined by the outer insulating layer.

公开(公告)号：US20230411321A1

公开(公告)日：2023-12-21

申请号：US18459628

申请日：2023-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngkyu LIM ,  Gookmi SONG ,  Sunguk LEE

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2924/3512

Abstract: A package substrate may include an insulation substrate, at least one redistribution layer (RDL) and a redistribution pad. The RDL may be included in the insulation substrate. The redistribution pad may extend from the RDL. The redistribution pad may include at least one segmenting groove in a radial direction of the redistribution pad. Thus, the at least one segmenting groove in the radial direction of the redistribution pad may reduce an area of the redistribution pad. Therefore, application of physical stress to a PID disposed over the redistribution pad may be suppressed, and thus generation of cracks in the PID may be reduced. Further, spreading of the cracks toward the redistribution pad from the PID may also be suppressed, and thus reliability the semiconductor package may be improved.

公开(公告)号：US20200273817A1

公开(公告)日：2020-08-27

申请号：US16703239

申请日：2019-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyujin CHOI ,  Sunghoan KIM ,  Changeun JOO ,  Chilwoo KWON ,  Youngkyu LIM ,  Sunguk LEE

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: The method of manufacturing a connection structure of a semiconductor chip includes: preparing a semiconductor chip having a first surface having a connection pad disposed thereon and a second surface opposing the first surface and including a passivation layer disposed on the first surface and covering the connection pad; forming an insulating layer on the first surface of the semiconductor chip, the insulating layer covering at least a portion of the passivation layer; forming a via hole penetrating through the insulating layer to expose at least a portion of the passivation layer; exposing at least a portion of the connection pad by removing the passivation layer exposed by the via hole; forming a redistribution via by filling the via hole with a conductive material; and forming a redistribution layer on the redistribution via and the insulating layer.

公开(公告)号：US20250079317A1

公开(公告)日：2025-03-06

申请号：US18813120

申请日：2024-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyeon SONG ,  Dongwon KANG ,  Sunguk LEE ,  Jaeean LEE ,  Gyujin CHOI

IPC: H01L23/532 ,  H01L23/14 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor package according to an embodiment includes a first substrate having an upper surface and a lower surface and a cavity extending from the upper surface to the lower surface; a first chip mounted in the cavity; a first redistribution structure disposed on the first chip; a passive element mounted inside the first redistribution structure; and an adhesive layer disposed below the passive element. The first redistribution structure includes a plurality of redistribution insulating layers stacked in a vertical direction on the first chip, and a first redistribution pattern and a second redistribution pattern located within the redistribution insulating layers. The first redistribution pattern is disposed below a recess vertically penetrating at least one redistribution insulating layer among the plurality of redistribution insulating layers. The second redistribution pattern is adjacent to the recess in a lateral direction.

公开(公告)号：US20210202414A1

公开(公告)日：2021-07-01

申请号：US16930517

申请日：2020-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngkyu LIM ,  Gookmi SONG ,  Sunguk LEE

IPC: H01L23/00

Abstract: A package substrate may include an insulation substrate, at least one redistribution layer (RDL) and a redistribution pad. The RDL may be included in the insulation substrate. The redistribution pad may extend from the RDL. The redistribution pad may include at least one segmenting groove in a radial direction of the redistribution pad. Thus, the at least one segmenting groove in the radial direction of the redistribution pad may reduce an area of the redistribution pad. Therefore, application of physical stress to a PID disposed over the redistribution pad may be suppressed, and thus generation of cracks in the PID may be reduced. Further, spreading of the cracks toward the redistribution pad from the PID may also be suppressed, and thus reliability the semiconductor package may be improved.