公开(公告)号：US20230205449A1

公开(公告)日：2023-06-29

申请号：US17680773

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WONSEB JEONG ,  YANG SEOK KI ,  JUNGMIN SEO ,  BEOMKYU SHIN ,  SANGOAK WOO ,  YOUNGGEON YOO ,  CHANHO YOON ,  MYUNGJUNE JUNG

IPC: G06F3/06 ,  G06F12/0802

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0802 ,  G06F2212/60

Abstract: A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.

公开(公告)号：US20230266917A1

公开(公告)日：2023-08-24

申请号：US17852022

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYEOKJUN CHOE ,  JEONGHO LEE ,  YOUNGGEON YOO ,  WONSEB JEONG

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0604

Abstract: A storage system includes a host and a storage device. The host includes a host processor and a host memory buffer, wherein the host processor includes a CPU core controlling operation of the host and a cache dedicated for use by the CPU core. The host memory buffer includes a submission queue and a completion queue. The storage device is connected to the host through a link and communicates with the host using a transaction layer packet (TLP). The storage device includes a nonvolatile memory device (NVM) and a storage controller, wherein the host writes a nonvolatile memory express (NVMe) command indicating a destination to the submission queue, and the storage controller reads data from the NVM, directly accesses the cache in response to destination information associated with the destination, and stores the read data in the cache.

公开(公告)号：US20230100573A1

公开(公告)日：2023-03-30

申请号：US17742184

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WONSEB JEONG ,  HEE HYUN NAM ,  YOUNGGEON YOO ,  JEONGHO LEE ,  YOUNHO JEON ,  IPOOM JEONG ,  CHANHO YOON

IPC: G06F3/06

Abstract: A memory device includes; a first memory of first type, a second memory of second type different from the first type, and a memory controller. The memory controller receives an access request and workload information related to work of an external processor, processes the access request using the workload information, and accesses at least one of the first memory and the second memory in response to the access request.