公开(公告)号：US20230205449A1

公开(公告)日：2023-06-29

申请号：US17680773

申请日：2022-02-25

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： WONSEB JEONG ,  YANG SEOK KI ,  JUNGMIN SEO ,  BEOMKYU SHIN ,  SANGOAK WOO ,  YOUNGGEON YOO ,  CHANHO YOON ,  MYUNGJUNE JUNG

IPC分类号： G06F3/06 ,  G06F12/0802

CPC分类号： G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0802 ,  G06F2212/60

摘要： A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.

公开(公告)号：US20230100573A1

公开(公告)日：2023-03-30

申请号：US17742184

申请日：2022-05-11

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： WONSEB JEONG ,  HEE HYUN NAM ,  YOUNGGEON YOO ,  JEONGHO LEE ,  YOUNHO JEON ,  IPOOM JEONG ,  CHANHO YOON

IPC分类号： G06F3/06

摘要： A memory device includes; a first memory of first type, a second memory of second type different from the first type, and a memory controller. The memory controller receives an access request and workload information related to work of an external processor, processes the access request using the workload information, and accesses at least one of the first memory and the second memory in response to the access request.

公开(公告)号：US20210125045A1

公开(公告)日：2021-04-29

申请号：US16854942

申请日：2020-04-22

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： JAEHUN JANG ,  HONGRAK SON ,  CHANGYU SEOL ,  GEUNYEONG YU ,  CHANHO YOON ,  PILSANG YOON

IPC分类号： G06N3/063 ,  G06N3/04 ,  H01L25/065 ,  H01L25/18

摘要： A stacked neuromorphic device includes a logic die including a control circuit and configured to communicate with a host, and core dies stacked on the logic die and connected to the logic die via through silicon vias (TSVs) extending through the core dies. The core dies include a neuromorphic core die including a synapse array connected to row lines and column lines. The synapse array includes synapses configured to store weights and perform a calculation based on the weights and input data. The weights are included in layers of a neural network system. And the control circuit provides the weights to the neuromorphic core die through the TSVs and controls data transmission by the neuromorphic core die.