公开(公告)号：US10665607B1

公开(公告)日：2020-05-26

申请号：US16251782

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kenji Sugiura ,  Mitsuteru Mushiga ,  Yuji Fukano ,  Akio Nishida

IPC: H01L27/11582 ,  H01L27/105 ,  H01L27/108 ,  H01L23/522 ,  H01L27/11568 ,  H01L21/768 ,  H01L27/11556

Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.

公开(公告)号：US10892267B2

公开(公告)日：2021-01-12

申请号：US15950616

申请日：2018-04-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Kenji Sugiura ,  Hisakazu Otoi ,  Shigehisa Inoue ,  Yuki Fukuda

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573 ,  H01L21/28 ,  H01L27/11565 ,  H01L27/11575 ,  H01L21/762 ,  H01L27/11519 ,  H01L27/11526

Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-protruding portion of the contact via structure contacts an annular top surface of the electrically conductive layer. The electrical isolation can be provided by a ribbed insulating spacer that includes laterally-protruding annular rib regions at levels of the insulating layers, or can be provided by annular insulating spacers located at levels of the electrically conductive layers. The contact via structure can contact a top surface of an underlying metal interconnect structure that overlies a substrate to provide an electrically conductive path.

公开(公告)号：US10586803B2

公开(公告)日：2020-03-10

申请号：US16023289

申请日：2018-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kenji Sugiura ,  Zhixin Cui ,  Kiyohiko Sakakibara

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11565 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11519

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.

公开(公告)号：US20190326307A1

公开(公告)日：2019-10-24

申请号：US16023866

申请日：2018-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kenji Sugiura

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.

公开(公告)号：US10797070B2

公开(公告)日：2020-10-06

申请号：US16241221

申请日：2019-01-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Kenji Sugiura ,  Akio Nishida

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/3213 ,  H01L27/1157 ,  H01L21/28

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures. The source-level semiconductor material layer may be electrically isolated from a substrate semiconductor material layer in the substrate by a series connection of two p-n junctions having opposite polarities.

公开(公告)号：US20190326306A1

公开(公告)日：2019-10-24

申请号：US16023289

申请日：2018-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kenji Sugiura ,  Zhixin Cui ,  Kiyohiko Sakakibara

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/28

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.

公开(公告)号：US10833100B2

公开(公告)日：2020-11-10

申请号：US16816552

申请日：2020-03-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kenji Sugiura ,  Mitsuteru Mushiga ,  Yuji Fukano ,  Akio Nishida

IPC: H01L27/11582 ,  H01L21/768 ,  H01L27/11568 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/105 ,  H01L27/108

Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.

公开(公告)号：US20190326313A1

公开(公告)日：2019-10-24

申请号：US16024048

申请日：2018-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Kiyohiko Sakakibara ,  Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kenji Sugiura

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/28

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.

公开(公告)号：US10354987B1

公开(公告)日：2019-07-16

申请号：US15928340

申请日：2018-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Akio Nishida ,  Kenji Sugiura ,  Hisakazu Otoi ,  Masatoshi Nishikawa

IPC: H01L25/00 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/18 ,  H01L27/11582 ,  H01L27/11556

Abstract: Sacrificial pillar structures are formed through a first semiconductor substrate on which first semiconductor devices are subsequently formed. After backside thinning of the first semiconductor substrate, the sacrificial pillar structures are replaced with integrated through-substrate via and pad structures to provide a first semiconductor chip. A second semiconductor chip is provided, which includes a second semiconductor substrate, second semiconductor devices, and second bonding pad structures electrically connected to a respective one of the second semiconductor devices. The first bonding pad structures are bonded to a respective one of the second bonding pad structures by surface activated bonding.

公开(公告)号：US10354980B1

公开(公告)日：2019-07-16

申请号：US15928407

申请日：2018-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Akio Nishida ,  Kenji Sugiura ,  Hisakazu Otoi ,  Masatoshi Nishikawa

IPC: H01L25/00 ,  H01L25/065 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/00 ,  H01L21/822

Abstract: Multiple semiconductor chips can be bonded through copper-to-copper bonding. The multiple semiconductor chips include a logic chip and multiple memory chips. The logic chip includes a peripheral circuitry for operation of memory devices within the multiple memory chips. The memory chips can include front side bonding pad structures, backside bonding pad structures, and sets of metal interconnect structures providing electrically conductive paths between pairs of a first side bonding pad structure and a backside bonding pad structure. Thus, electrical control signal can vertically propagate between the logic chip and an overlying memory chip through at least one intermediate memory chip located between them. The backside bonding pad structures can be formed as portions of integrated through-substrate via and pad structures that extend through a respective semiconductor substrate.