公开(公告)号：US11210241B1

公开(公告)日：2021-12-28

申请号：US17068957

申请日：2020-10-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nitin Gupta ,  Ashish Savadia ,  Jayanth Thimmaiah ,  Ramakrishnan Subramanian ,  Rampraveen Somasundaram ,  Shiv Harit Mathur ,  Vinayak Ghatawade ,  Siddesh Darne ,  Venkatesh Ramachandra ,  Elkana Richter

IPC: G06F13/16 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

Abstract: A data storage system includes a storage medium including plurality of memory cells, a storage controller in communication with the storage medium, an electrical interface circuitry configured to pass data via a channel disposed between the storage medium and the storage controller; and voltage training circuitry configured to train a high-level output voltage (VOH) for each of a plurality of data lines of the channel. Training the VOH includes, for each of the plurality of data lines of the channel, calibrating a pull-up driver of the storage controller against an on-die termination circuit of the storage medium, calibrating a pull-down driver of the storage controller against the pull-up driver of the storage controller, and calibrating an on-die termination circuit of the storage controller against a pull-up driver of the storage medium.

公开(公告)号：US10129012B2

公开(公告)日：2018-11-13

申请号：US15473067

申请日：2017-03-29

Applicant: SanDisk Technologies LLC

Inventor： Krishnamurthy Dhakshinamurthy ,  Shajith Musaliar Sirajudeen ,  Jayaprakash Naradasi ,  Bhavin Odedara ,  Yosi Pinto ,  Rampraveen Somasundaram ,  Anand Sharma

IPC: H04L7/00

Abstract: A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.

公开(公告)号：US20180083764A1

公开(公告)日：2018-03-22

申请号：US15473067

申请日：2017-03-29

Applicant: SanDisk Technologies LLC

Inventor： Krishnamurthy Dhakshinamurthy ,  Shajith Musaliar Sirajudeen ,  Jayaprakash Naradasi ,  Bhavin Odedara ,  Yosi Pinto ,  Rampraveen Somasundaram ,  Anand Sharma

IPC: H04L7/00

CPC classification number: H04L7/0012 ,  G06F1/12 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0337

Abstract: A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.