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    Duty cycle and vox correction for complementary signals
    2.
    发明授权
    Duty cycle and vox correction for complementary signals 有权

    公开(公告)号：US10587247B2

    公开(公告)日：2020-03-10

    申请号：US15875519

    申请日：2018-01-19

    Applicant: SanDisk Technologies LLC

    Inventor： Tianyu Tang ,  Venkatesh Ramachandra ,  Srinivas Rajendra

    IPC: H03K3/017 ,  H03K17/687 ,  H03M1/66

    Abstract: A correction system is configured to correct for duty cycle distortion and/or cross-point distortion in a pair of sample signals. A slope adjustment circuit is configured to generate a plurality of pairs of intermediate signals according to a plurality of drive strengths. A measurement circuit is configured to measure for duty cycle distortion and/or cross-point distortion, and the slope adjustment circuit is configured to set the plurality of drive strengths based on the measurement. The setting of the drive strengths may reduce certain rising and falling slopes of certain transitions of the plurality of intermediate signals, which in turn may reduce duty cycle distortion and/or cross-point distortion in the sample signals.

    Per pin Vref for data receivers in non-volatile memory system
    3.
    发明授权
    Per pin Vref for data receivers in non-volatile memory system 有权

    公开(公告)号：US11482262B1

    公开(公告)日：2022-10-25

    申请号：US17348904

    申请日：2021-06-16

    Applicant: SanDisk Technologies LLC

    Inventor： Jang Woo Lee ,  Srinivas Rajendra ,  Anil Pai ,  Venkatesh Ramachandra

    IPC: G06F13/16 ,  G11C7/10 ,  G06F13/40

    Abstract: Technology is disclosed herein for per pin internal reference voltage generation for data receivers in non-volatile memory systems. A receiving circuit may have an on-die voltage generator that has inputs to receive a separate voltage magnitude select signal for each data receiver on the receiving circuit. The on-die voltage generator provides a separate reference voltage for each data receiver. This allows the reference voltage for each data receiver to be calibrated separately. A separate reference voltage for each data receiver compensates for variations between data paths, and provides for a wider data valid window than if the same reference voltage were used for all data receivers. Generating the different reference voltages on-die can potentially require a large area, as well as consume considerable power and/or current. A voltage divider and multiplexers may provide the different reference voltages, which saves space and is power and current efficient.

    DUTY CYCLE AND VOX CORRECTION FOR COMPLEMENTARY SIGNALS
    4.
    发明申请
    DUTY CYCLE AND VOX CORRECTION FOR COMPLEMENTARY SIGNALS 审中-公开

    公开(公告)号：US20190109585A1

    公开(公告)日：2019-04-11

    申请号：US15875519

    申请日：2018-01-19

    Applicant: SanDisk Technologies LLC

    Inventor： Tianyu Tang ,  Venkatesh Ramachandra ,  Srinivas Rajendra

    IPC: H03K3/017 ,  H03K17/687 ,  H03M1/66

    Abstract: A correction system is configured to correct for duty cycle distortion and/or cross-point distortion in a pair of sample signals. A slope adjustment circuit is configured to generate a plurality of pairs of intermediate signals according to a plurality of drive strengths. A measurement circuit is configured to measure for duty cycle distortion and/or cross-point distortion, and the slope adjustment circuit is configured to set the plurality of drive strengths based on the measurement. The setting of the drive strengths may reduce certain rising and falling slopes of certain transitions of the plurality of intermediate signals, which in turn may reduce duty cycle distortion and/or cross-point distortion in the sample signals.

    SEMI RECEIVER SIDE WRITE TRAINING FOR NON-VOLATILE MEMORY SYSTEM
    7.
    发明申请
    SEMI RECEIVER SIDE WRITE TRAINING FOR NON-VOLATILE MEMORY SYSTEM 有权

    公开(公告)号：US20220405190A1

    公开(公告)日：2022-12-22

    申请号：US17348910

    申请日：2021-06-16

    Applicant: SanDisk Technologies LLC

    Inventor： Jang Woo Lee ,  Srinivas Rajendra ,  Anil Pai ,  Venkatesh Ramachandra

    IPC: G06F11/36 ,  G06K9/62

    Abstract: Technology is disclosed herein for semi receiver side write training in a non-volatile memory system. The transmitting device has delay taps that control the delay between a data strobe signal and data signals sent on the communication bus. The delay taps on the transmitting device are more precise that can typically be fabricated on the receiving device (e.g., NAND memory die). However, the receiving device performs the comparisons between test data and expected data, which alleviates the need to read back the test data. After the different delays have been tested, the receiving device informs the transmitting device of the shortest and longest delays for which data was validly received. The transmitting device then sets the delay taps based on this information. Moreover, the write training can be performed in parallel on many receiving devices, which is very efficient.

    DUTY CYCLE CORRECTION FOR COMPLEMENTARY CLOCK SIGNALS
    8.
    发明申请
    DUTY CYCLE CORRECTION FOR COMPLEMENTARY CLOCK SIGNALS 审中-公开

    公开(公告)号：US20200076412A1

    公开(公告)日：2020-03-05

    申请号：US16206321

    申请日：2018-11-30

    Applicant: SanDisk Technologies LLC

    Inventor： Srinivas Rajendra ,  Tianyu Tang ,  Venkatesh Ramachandra

    IPC: H03K5/156 ,  H03K5/134 ,  G11C7/22 ,  G11C11/4076 ,  H01L27/11524

    Abstract: A duty cycle correction circuit includes an AND/OR logic circuit that reduces duty cycle distortion in a pair of input signals. The AND/OR logic circuit includes a first push-pull circuit configured to generate a first output signal in response to receipt of a first pair of delayed input signals, and a second push-pull circuit configured to generate a second output signal in response to receipt of a second pair of delayed input signals. The first and second push-pull circuits may have matching beta ratios. Additionally, a latch is coupled to output nodes of the first and second push-pull circuits. The latch is configured to maintain magnitude levels at the output nodes during delay offset periods of the first and second pairs of delayed input signals.

    Duty cycle correction on an interval-by-interval basis
    9.
    发明授权
    Duty cycle correction on an interval-by-interval basis 有权

    公开(公告)号：US10447247B1

    公开(公告)日：2019-10-15

    申请号：US15965099

    申请日：2018-04-27

    Applicant: SanDisk Technologies LLC

    Inventor： Tianyu Tang ,  Venkatesh Ramachandra

    IPC: H03K3/017 ,  G11C7/22

    Abstract: A duty cycle correction system corrects for duty cycle distortion by measuring average time interval durations of consecutive intervals of an input signal. The system generates complementary ramp signals that have cross-points indicating midpoints of the intervals, and detects those cross-points. An output circuit of the duty cycle correction system generates an output signal that performs rising and falling transitions in response to the detected cross-points.

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