公开(公告)号：US09768186B2

公开(公告)日：2017-09-19

申请号：US15216941

申请日：2016-07-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seiji Shimabukuro ,  Ryoichi Honma ,  Hiroyuki Ogawa ,  Yuki Mizutani ,  Fumiaki Toyama

IPC: G11C16/04 ,  H01L27/115 ,  H01L21/768 ,  H01L23/528 ,  H01L29/788 ,  H01L29/06 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/66 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11575 ,  H01L23/522 ,  H01L27/11551 ,  G11C5/02 ,  H01L29/792

CPC classification number: H01L27/11556 ,  G11C5/02 ,  G11C16/0408 ,  G11C16/0483 ,  G11C2213/71 ,  H01L23/5226 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A monolithic three dimensional memory device includes a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate, a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate, and a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member including an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region.

公开(公告)号：US09978768B2

公开(公告)日：2018-05-22

申请号：US15196714

申请日：2016-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jiyin Xu ,  Ryoichi Honma ,  Syo Fukata

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L21/02 ,  H01L27/11573

CPC classification number: H01L27/1157 ,  H01L21/02063 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A method of manufacturing a semiconductor device includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a substrate, forming a memory opening through the stack, forming a layer stack including a memory material layer, a tunneling dielectric layer, and a first semiconductor material layer in the memory opening, forming a protective layer over the first semiconductor channel layer, physically exposing a semiconductor surface underneath the layer stack by anisotropically etching horizontal portions of the protective layer and the layer stack at a bottom portion of the memory opening, removing a remaining portion of the protective layer selective to the first semiconductor channel layer, and forming a second semiconductor channel layer on the first semiconductor channel layer.

公开(公告)号：US20160329341A1

公开(公告)日：2016-11-10

申请号：US15216941

申请日：2016-07-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seiji Shimabukuro ,  Ryoichi Honma ,  Hiroyuki Ogawa ,  Yuki Mizutani ,  Fumiaki Toyama

IPC: H01L27/115 ,  H01L23/522

CPC classification number: H01L27/11556 ,  G11C5/02 ,  G11C16/0408 ,  G11C16/0483 ,  G11C2213/71 ,  H01L23/5226 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A monolithic three dimensional memory device includes a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate, a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate, and a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member including an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region.

Abstract translation: 单片三维存储器件包括具有基本上平行于半导体衬底的主表面延伸的第一导电类型的主表面和掺杂阱区的半导体衬底，多个NAND存储器串，基本上垂直于半导体衬底的主表面延伸 所述半导体衬底以及基本上垂直于所述半导体衬底的主表面延伸的多个基本上柱状的支撑构件，每个支撑构件包括围绕导电芯材的电绝缘外部材料，所述导电芯材基本上垂直于所述半导体衬底的主表面延伸 半导体衬底并与掺杂阱区电接触。