公开(公告)号：US20150349133A1

公开(公告)日：2015-12-03

申请号：US14813408

申请日：2015-07-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Ryosuke WATANABE ,  Masashi OOTA ,  Noritaka ISHIHARA ,  Koki INOUE

IPC: H01L29/786

CPC classification number: H01L29/1054 ,  H01L22/14 ,  H01L29/247 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10−3/cm in an energy range of 1.5 eV to 2.3 eV.

公开(公告)号：US20220292332A1

公开(公告)日：2022-09-15

申请号：US17629499

申请日：2020-07-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yusuke KOUMURA ,  Koki INOUE ,  Ayana KIMOTSUKI ,  Fumiya NAGASHIMA

IPC: G06N3/04 ,  G06T7/50 ,  G06T1/60 ,  G06N3/063

Abstract: A system with high processing speed and low power consumption is provided. The system includes an imaging device and an arithmetic circuit. The imaging device includes an imaging portion, a first memory portion, and an arithmetic portion, and the arithmetic circuit includes a second memory portion. The imaging portion has a function of converting light reflected by an external subject into image data, and the first memory portion has a function of storing the image data and a first filter for performing first convolutional processing in a first layer of a neural network. The arithmetic portion has a function of performing the first convolutional processing using the image data and the first filter to generate first data. The second memory portion has a function of storing the first data and a plurality of filters. The arithmetic circuit has a function of generating a depth map of the image data.

公开(公告)号：US20230024698A1

公开(公告)日：2023-01-26

申请号：US17783074

申请日：2020-12-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yusuke KOUMURA ,  Koki INOUE ,  Fumiya NAGASHIMA

IPC: G06N3/04 ,  G06N3/08 ,  G06V10/776 ,  G06V10/82

Abstract: A neural network model that can perform highly accurate processing on input data is provided. The neural network model includes first and second neutral networks, and the first neural network includes a first layer, a second layer, and a third layer. A feature map output from the first layer is input to the second layer and the second neural network, and a feature map output from the second neural network is input to the third layer. Given that the feature map output from the first layer when first data is input to the first neural network is a correct feature map and that the feature map output from the first layer when second data obtained by adding noise to the first data is input to the first neural network is a learning feature map, the second neural network is learned so that a feature map output from the second neural network matches the correct feature map when the learning feature map is input.

公开(公告)号：US20220237275A1

公开(公告)日：2022-07-28

申请号：US17615257

申请日：2020-06-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shigeru TAMAKI ,  Kengo AKIMOTO ,  Hiromichi GODO ,  Koki INOUE ,  Yoshitaka DOZEN ,  Shunpei YAMAZAKI

IPC: G06F21/32 ,  G06F21/60 ,  G06N20/00

Abstract: An authentication system for an electronic device with a high security level is provided. The authentication system includes a data retention means that accumulates first data related to a state of the electronic device being used by a first user registered in advance and generates a first data group, a first authentication means that authenticates a second user operating the electronic device as the first user and releases a locked state, a data acquisition means that acquires second data related to a state of the electronic device being used by the second user in a state where the locked state is released, and a second authentication means that authenticates the second user as the first user on the basis of the first data group and the second data and sets the electronic device to the locked state when the second user is not authenticated. The data retention means has a function of deleting the oldest first data of the plurality of pieces of the first data included in the first data group.

公开(公告)号：US20150048368A1

公开(公告)日：2015-02-19

申请号：US14527076

申请日：2014-10-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Ryosuke WATANABE ,  Masashi OOTA ,  Noritaka ISHIHARA ,  Koki INOUE

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/1054 ,  H01L22/14 ,  H01L29/247 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10−3/cm in an energy range of 1.5 eV to 2.3 eV.

Abstract translation: 提供了不容易引起晶体管的电特性变化并且具有高稳定性的氧化物半导体层叠膜。 此外，提供了在其沟道形成区域中包括氧化物半导体层叠膜并且具有稳定的电特性的晶体管。 氧化物半导体层叠膜包括依次堆叠并且各自含有铟，镓和锌的第一氧化物半导体层，第二氧化物半导体层和第三氧化物半导体层。 第二氧化物半导体层中的铟的含量百分比高于第一氧化物半导体层和第三氧化物半导体层中的铟的含量百分比，并且通过CPM测量的氧化物半导体层叠膜的吸收系数低于或等于 在1.5eV至2.3eV的能量范围内等于3×10-3 / cm。

公开(公告)号：US20140034946A1

公开(公告)日：2014-02-06

申请号：US13953428

申请日：2013-07-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Ryosuke WATANABE ,  Masashi OOTA ,  Noritaka ISHIHARA ,  Koki INOUE

IPC: H01L29/24 ,  H01L29/786

CPC classification number: H01L29/1054 ,  H01L22/14 ,  H01L29/247 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10−3/cm in an energy range of 1.5 eV to 2.3 eV.

Abstract translation: 提供了不容易引起晶体管的电特性变化并且具有高稳定性的氧化物半导体层叠膜。 此外，提供了在其沟道形成区域中包括氧化物半导体层叠膜并且具有稳定的电特性的晶体管。 氧化物半导体层叠膜包括依次堆叠并且各自含有铟，镓和锌的第一氧化物半导体层，第二氧化物半导体层和第三氧化物半导体层。 第二氧化物半导体层中的铟的含量百分比高于第一氧化物半导体层和第三氧化物半导体层中的铟的含量百分比，并且通过CPM测量的氧化物半导体层叠膜的吸收系数低于或等于 在1.5eV至2.3eV的能量范围内等于3×10-3 / cm。

公开(公告)号：US20230044180A1

公开(公告)日：2023-02-09

申请号：US17792053

申请日：2021-01-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kengo AKIMOTO ,  Koki INOUE ,  Yusuke KOUMURA

IPC: G06T3/40 ,  G06T7/11 ,  G06T7/50 ,  G06V10/25 ,  G06V10/82 ,  H04N9/43 ,  B60W40/105

Abstract: The driving assistance system includes an imaging device capable of capturing a first monochrome image in a vehicle traveling direction, a first neural network for segmentation processing, a second neural network for depth estimation processing, a determination portion determining a center of a portion cut off from the first monochrome image on the basis of the segmentation processing and the depth estimation processing, a third neural network for colorization processing of only a second cut-off monochrome image, and a display device for enlargement of the second monochrome image subjected to the colorization processing.

公开(公告)号：US20220365587A1

公开(公告)日：2022-11-17

申请号：US17629866

申请日：2020-07-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Koki INOUE ,  Ryo NAKAZATO ,  Daichi MISHIMA

IPC: G06F1/3296 ,  G06F1/04

Abstract: A data processing system having high reliability and an operation method thereof are provided. The data processing system includes an arithmetic processing device including a nonvolatile memory and/or a nonvolatile register, and a monitoring system for monitoring an operation state of the arithmetic processing device. The monitoring system is a system utilizing artificial intelligence, and has a function of estimating from a program operating on the arithmetic processing device how much and which location of the arithmetic processing device will increase in temperature when the program operates. When the monitoring system estimates that the temperature of part of the arithmetic processing device will exceed a threshold value when the program operates, the monitoring system transmits an instruction to lower a clock frequency of the part of the arithmetic processing device, reduce a power supply potential of the part, or interrupt power supply to the part.

公开(公告)号：US20150069393A1

公开(公告)日：2015-03-12

申请号：US14547285

申请日：2014-11-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi TSUBUKU ,  Takayuki INOUE ,  Suzunosuke HIRAISHI ,  Erumu KIKUCHI ,  Hiromichi GODO ,  Shuhei YOSHITOMI ,  Koki INOUE ,  Akiharu MIYANAGA ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/40

CPC classification number: H01L29/7869 ,  H01L29/408

Abstract: Manufactured is a transistor including an oxide semiconductor layer, a source electrode layer and a drain electrode layer overlapping with part of the oxide semiconductor layer, a gate insulating layer overlapping with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode overlapping with part of the oxide semiconductor layer with the gate insulating layer provided therebetween, wherein, after the oxide semiconductor layer which is to be a channel formation region is irradiated with light and the light irradiation is stopped, a relaxation time of carriers in photoresponse characteristics of the oxide semiconductor layer has at least two kinds of modes: τ1 and τ2, τ1

Abstract translation: 制造的是包括与氧化物半导体层的一部分重叠的氧化物半导体层，源极电极层和漏极电极层，与氧化物半导体层重叠的栅极绝缘层，源极电极层和漏极电极层的晶体管， 以及与所述氧化物半导体层的与氧化物半导体层的一部分重叠的栅电极，其间设置有栅极绝缘层，其中，在作为沟道形成区域的氧化物半导体层被照射光并停止光照射之后，弛豫时间 氧化物半导体层的光响应特性中的载流子具有至少两种模式：τ1和τ2，τ1<τ2，τ2为300秒以下。 此外，制造包括晶体管的半导体器件。