公开(公告)号：US20180233597A1

公开(公告)日：2018-08-16

申请号：US15946149

申请日：2018-04-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Toshihiko TAKEUCHI ,  Yasumasa YAMANE ,  Takayuki INOUE ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L27/1156

CPC classification number: H01L29/7869 ,  H01L27/1156 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A manufacturing method of a semiconductor device in which the threshold is adjusted to an appropriate value is provided. The semiconductor device includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is sandwiched, an electron trap layer between the first gate electrode and the semiconductor, and a gate insulating layer between the second gate electrode and the semiconductor. By keeping a potential of the first gate electrode higher than a potential of the source or drain electrode for 1 second or more while heating, electrons are trapped in the electron trap layer. Consequently, threshold is increased and Icut is reduced.

公开(公告)号：US20170317196A1

公开(公告)日：2017-11-02

申请号：US15605160

申请日：2017-05-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA ,  Toshihiko TAKEUCHI ,  Yasumasa YAMANE ,  Takayuki INOUE ,  Shunpei YAMAZAKI

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L29/4908 ,  H01L29/7869 ,  H01L29/78696

Abstract: A manufacturing method of a semiconductor device in which the threshold voltage is adjusted is provided. The semiconductor device includes a first semiconductor, an electrode electrically connected to the first semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the first semiconductor. By performing heat treatment at higher than or equal to 125 ° C. and lower than or equal to 450 ° C. and, at the same time, keeping a potential of the gate electrode higher than a potential of the electrode for 1 second or more, the threshold voltage is increased.

公开(公告)号：US20150060846A1

公开(公告)日：2015-03-05

申请号：US14471766

申请日：2014-08-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Hideomi SUZAWA

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/02 ,  H01L29/786 ,  H01L29/51

CPC classification number: H01L29/7869 ,  H01L21/0214 ,  H01L21/02181 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/28282 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31645 ,  H01L21/32136 ,  H01L21/441 ,  H01L21/465 ,  H01L21/473 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78693 ,  H01L29/78696 ,  H01L29/792

Abstract: A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P≧45−0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.

Abstract translation: 提供其中调整阈值的半导体器件。 在包括半导体，与半导体电连接的源电极或漏电极，栅电极和栅电极和半导体之间的电子捕获层的晶体管中，电子捕获层包括结晶的氧化铪。 通过使用氧化铪作为靶的溅射法沉积结晶的氧化铪。 溅射法中，衬底温度为Tsub（℃），气氛中氧的比例为P（％）时，P≥45〜0.15×Tsub。 结晶的氧化铪具有优异的电子捕获性能。 通过适当数量的电子的陷阱，可以调整半导体器件的阈值。

公开(公告)号：US20140246674A1

公开(公告)日：2014-09-04

申请号：US14278634

申请日：2014-05-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yusuke NONAKA ,  Takayuki INOUE ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Akiharu MIYANAGA

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/04 ,  H01L29/24 ,  H01L29/78603

Abstract: An object is to provide a semiconductor device including an oxide semiconductor film, which has stable electrical characteristics and high reliability. A stack of first and second material films is formed by forming the first material film (a film having a hexagonal crystal structure) having a thickness of 1 nm to 10 nm over an insulating surface and forming the second material film having a hexagonal crystal structure (a crystalline oxide semiconductor film) using the first material film as a nucleus. As the first material film, a material film having a wurtzite crystal structure (e.g., gallium nitride or aluminum nitride) or a material film having a corundum crystal structure (α-Al2O3, α-Ga2O3, In2O3, Ti2O3, V2O3, Cr2O3, or α-Fe2O3) is used.

Abstract translation: 本发明的目的是提供一种具有稳定的电气特性和高可靠性的氧化物半导体膜的半导体装置。 通过在绝缘表面上形成厚度为1nm至10nm的第一材料膜（具有六方晶体结构的膜）形成第一和第二材料膜的叠层，并形成具有六方晶系结构的第二材料膜（ 使用第一材料膜作为核的结晶氧化物半导体膜）。 作为第一材料膜，具有纤锌矿晶体结构的材料膜（例如氮化镓或氮化铝）或具有刚玉晶体结构的材料膜（α-Al 2 O 3，α-Ga 2 O 3，In 2 O 3，Ti 2 O 3，V 2 O 3，Cr 2 O 3，或 α-Fe 2 O 3）。

公开(公告)号：US20150340509A1

公开(公告)日：2015-11-26

申请号：US14819772

申请日：2015-08-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yusuke NONAKA ,  Takayuki INOUE ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Akiharu MIYANAGA

IPC: H01L29/786 ,  H01L29/04 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/04 ,  H01L29/24 ,  H01L29/78603

Abstract: An object is to provide a semiconductor device including an oxide semiconductor film, which has stable electrical characteristics and high reliability. A stack of first and second material films is formed by forming the first material film (a film having a hexagonal crystal structure) having a thickness of 1 nm to 10 nm over an insulating surface and forming the second material film having a hexagonal crystal structure (a crystalline oxide semiconductor film) using the first material film as a nucleus. As the first material film, a material film having a wurtzite crystal structure (e.g., gallium nitride or aluminum nitride) or a material film having a corundum crystal structure (α-Al2O3, α-Ga2O3, In2O3, Ti2O3, V2O3, Cr2O3, or α-Fe2O3) is used.

Abstract translation: 本发明的目的是提供一种具有稳定的电气特性和高可靠性的氧化物半导体膜的半导体装置。 通过在绝缘表面上形成厚度为1nm至10nm的第一材料膜（具有六方晶体结构的膜）形成第一和第二材料膜的叠层，并形成具有六方晶系结构的第二材料膜（ 使用第一材料膜作为核的结晶氧化物半导体膜）。 作为第一材料膜，具有纤锌矿晶体结构的材料膜（例如氮化镓或氮化铝）或具有刚玉晶体结构的材料膜（α-Al 2 O 3，α-Ga 2 O 3，In 2 O 3，Ti 2 O 3，V 2 O 3，Cr 2 O 3，或 α-Fe 2 O 3）。

公开(公告)号：US20150069385A1

公开(公告)日：2015-03-12

申请号：US14476767

申请日：2014-09-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L29/7869 ,  G11C7/04 ,  G11C11/24 ,  G11C14/0054 ,  G11C16/0466 ,  G11C16/3404 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696 ,  H01L29/7881

Abstract: A method for adjusting threshold of a semiconductor device is provided. In a plurality of semiconductor devices each including a semiconductor, a source or drain electrode electrically in contact with the semiconductor, a gate electrode, and a charge trap layer between a gate electrode and the semiconductor, a state where the potential of the gate electrode is set higher than the potential of the source or drain electrode while the semiconductor devices are heated at 150° C. or higher and 300° C. or lower is kept for one second or longer to trap electrons in the charge trap layer, so that the threshold is increased and Icut is reduced. Here, the potential difference between the gate electrode and the source or drain electrode is set so that it is different between the semiconductor devices, and the thresholds of the semiconductor devices are adjusted to be appropriate to each purpose.

Abstract translation: 提供了一种用于调整半导体器件的阈值的方法。 在多个半导体器件中，每个半导体器件包括半导体，与半导体电接触的源极或漏极，栅电极和栅电极与半导体之间的电荷陷阱层，栅电极的电位为 设定为高于源极或漏极的电位，同时将半导体器件在150℃以上且300℃以下的温度加热保持1秒以上以在电荷陷阱层中捕获电子，使得 阈值增加并且Icut减小。 这里，栅电极和源电极或漏电极之间的电位差被设定为在半导体器件之间不同，并且将半导体器件的阈值调整为适合于每个目的。

公开(公告)号：US20150011046A1

公开(公告)日：2015-01-08

申请号：US14313145

申请日：2014-06-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA ,  Toshihiko TAKEUCHI ,  Yasumasa YAMANE ,  Takayuki INOUE ,  Shunpei YAMAZAKI

IPC: H01L29/66

CPC classification number: H01L29/66969 ,  H01L29/4908 ,  H01L29/7869 ,  H01L29/78696

Abstract: A manufacturing method of a semiconductor device in which the threshold voltage is adjusted is provided. The semiconductor device includes a first semiconductor, an electrode electrically connected to the first semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the first semiconductor. By performing heat treatment at higher than or equal to 125° C. and lower than or equal to 450° C. and, at the same time, keeping a potential of the gate electrode higher than a potential of the electrode for 1 second or more, the threshold voltage is increased.

Abstract translation: 提供其中调整阈值电压的半导体器件的制造方法。 半导体器件包括第一半导体，电连接到第一半导体的电极，栅极电极和栅电极和第一半导体之间的电子陷阱层。 通过进行高于或等于125℃且低于或等于450℃的热处理，并且同时保持栅电极的电位高于电极的电位1秒以上 ，阈值电压增加。

公开(公告)号：US20150069387A1

公开(公告)日：2015-03-12

申请号：US14479623

申请日：2014-09-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Hideomi SUZAWA ,  Yasuhiko TAKEMURA

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  G11C11/24 ,  G11C16/00 ,  G11C16/0466 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78696 ,  H01L29/7881

Abstract: A method for manufacturing a semiconductor device with adjusted threshold is provided. In a semiconductor device including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is provided, a charge trap layer provided between the first gate electrode and the semiconductor, and a gate insulating layer provided between the second gate electrode and the semiconductor, a threshold is increased by trapping electrons in the charge trap layer by keeping a potential of the first gate electrode at a potential higher than a potential of the source or drain electrode for 1 second or more while heating. After the threshold adjustment process, the first gate electrode is removed or insulated from other circuits. Alternatively, a resistor may be provided between the first gate electrode and other circuits.

Abstract translation: 提供一种用于制造具有调节阈值的半导体器件的方法。 在包括半导体，与半导体电连接的源电极或漏电极的半导体器件中，设置有半导体的第一栅电极和第二栅电极，设置在第一栅电极和半导体之间的电荷陷阱层，以及 设置在第二栅电极和半导体之间的栅极绝缘层，通过将第一栅电极的电位保持在高于源电极或漏电极的电位的电位为1，通过在电荷陷阱层中俘获电子来增加阈值 第二次或多次加热。 在阈值调整处理之后，第一栅电极被去除或与其它电路绝缘。 或者，可以在第一栅极电极和其它电路之间设置电阻器。

公开(公告)号：US20150054548A1

公开(公告)日：2015-02-26

申请号：US14464966

申请日：2014-08-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Yasuhiko TAKEMURA ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Toshihiko TAKEUCHI ,  Yasumasa YAMANE ,  Shunpei YAMAZAKI

IPC: H03K19/00 ,  H01L21/324 ,  H01L27/115 ,  H03K19/003 ,  H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/1225 ,  H01L29/4234 ,  H01L29/66833 ,  H03K19/0013 ,  H03K19/17736

Abstract: A manufacturing method of a semiconductor device in which the threshold is adjusted is provided. In a semiconductor device including a plurality of transistors arranged in a matrix each including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit that supplies a signal to the gate electrode (e.g., word line driver) is provided with a selection circuit formed of an OR gate, an XOR gate, or the like, whereby potentials of word lines can be simultaneously set higher than potentials of bit lines.

Abstract translation: 提供了其中调整阈值的半导体器件的制造方法。 在包括以矩阵形式排列的多个晶体管的半导体器件中，每个晶体管包括半导体，与该半导体电连接的源极或漏极，栅电极和栅电极与半导体之间的电荷陷阱层，电子被俘获在 通过进行热处理，同时使栅电极的电位比源极或漏极的电位高1秒以上。 通过该过程，阈值增加并且Icut减小。 向门电极（例如字线驱动器）提供信号的电路设置有由或门，异或门等形成的选择电路，由此可以将字线的电位同时设置为高于电位 位线。

公开(公告)号：US20150024544A1

公开(公告)日：2015-01-22

申请号：US14508075

申请日：2014-10-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yusuke NONAKA ,  Takayuki INOUE ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Akiharu MIYANAGA

IPC: H01L29/66 ,  H01L23/00 ,  H01L23/552

CPC classification number: H01L29/78606 ,  H01L23/552 ,  H01L23/564 ,  H01L29/04 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor film, which has stable electric characteristics and high reliability. A crystalline oxide semiconductor film is formed, without performing a plurality of steps, as follows: by utilizing a difference in atomic weight of plural kinds of atoms included in an oxide semiconductor target, zinc with low atomic weight is preferentially deposited on an oxide insulating film to form a seed crystal including zinc; and tin, indium, or the like with high atomic weight is deposited on the seed crystal while causing crystal growth. Further, a crystalline oxide semiconductor film is formed by causing crystal growth using a seed crystal with a hexagonal crystal structure including zinc as a nucleus, whereby a single crystal oxide semiconductor film or a substantially single crystal oxide semiconductor film is formed.