公开(公告)号：US20150016492A1

公开(公告)日：2015-01-15

申请号：US14363954

申请日：2012-12-20

Applicant: ST-Ericsson SA

Inventor： Kimmo Koli

IPC: H04B15/00 ,  H04W84/12 ,  H04B1/40

CPC classification number: H04B15/00 ,  H03H19/008 ,  H04B1/40 ,  H04W84/12

Abstract: A signal filter (100) comprises a first transferred impedance filter, TIF, (TIFA) having four differential signal paths (PA,1, PA,2, PA,3, PA,4) and a second TIF (TIFB) having four differential signal paths (PB,1, PB,2, PB,3, PB,4)−. A first differential signal port of the first TIF (32A) is coupled to a first differential signal port of the second TIF (32B). A first clock generator (12A) is arranged to provide first-TIF clock signals (CLKA,I+, CLKA,Q+, CLKA,I−, CLKA,Q−) having four non-overlapping phases for selecting the respective first-TIF differential signal paths (PA,1, PA,2, PA,3, PA,4), and a second clock generator (12B) is arranged to provide second-TIF clock signals (CLKB,I+, CLKB,Q+, CLKB,J−, CLKB,Q−) having four non-overlapping phases for selecting the respective second-TIF differential signal paths (PB,1, PB,2, PB,3, PB,4). The phases of the second-TIF clock signals (CLKB,I+, CLKB,Q+, CLKB,Q−) are equal to the phases of the first-TIF clock signals (CLKA,I+, CLKA,Q+, CLKA,I−, CLKA,Q−) delayed by 45 degrees. The first-TIF first, second, third and fourth clock signals (CLKA,I+, CLKA,Q+, CLKA,I−L, CLKAQ−) and the second-TIF first, second, third and fourth clock signals (CLKB,I+, CLKB,Q+, CLKB,I−, CLKB,Q−) have a duty cycle in the range 16.75% to 25%.

Abstract translation: 信号滤波器（100）包括具有四个差分信号路径（PA，1，PA，2，PA，3，PA，4）和具有四个差分信号的第二TIF（TIFB）的第一传输阻抗滤波器TIF（TIFA） 信号路径（PB，1，PB，2，PB，3，PB，4） - 。 第一TIF（32A）的第一差分信号端口耦合到第二TIF（32B）的第一差分信号端口。 第一时钟发生器（12A）被布置成提供具有四个非重叠相位的第一TIF时钟信号（CLKA，I +，CLKA，Q +，CLKA，I，CLKA，Q-），用于选择相应的第一TIF差分信号 路径（PA，1，PA，2，PA，3，PA，4）和第二时钟发生器（12B）被布置成提供第二TIF时钟信号（CLKB，I +，CLKB，Q +，CLKB，J-， CLKB，Q-）具有用于选择相应的第二TIF差分信号路径（PB，1，PB，2，PB，3，PB，4）的四个非重叠相位。 第二TIF时钟信号（CLKB，I +，CLKB，Q +，CLKB，Q-）的相位等于第一TIF时钟信号（CLKA，I +，CLKA，Q +，CLKA，I，CLKA）的相位 ，Q-）延迟45度。 第一TIF第一，第二，第三和第四时钟信号（CLKA，I +，CLKA，Q +，CLKA，I-L，CLKAQ-）和第二TIF第一，第二，第三和第四时钟信号（CLKB，I + CLKB，Q +，CLKB，I，CLKB，Q-）的占空比在16.75％至25％的范围内。

公开(公告)号：US20140368368A1

公开(公告)日：2014-12-18

申请号：US14368040

申请日：2012-12-29

Applicant: ST-Ericsson SA

Inventor： Kimmo Koli

IPC: H03M3/00 ,  H03M1/06

CPC classification number: H03M3/462 ,  H03M1/06 ,  H03M3/394 ,  H03M3/414 ,  H03M3/436 ,  H03M3/496

Abstract: Continuous-time MASH sigma-delta ADC with a first modulator with 1.5 bit and a second modulator with 1 bit each receiving also the feedback from the other modulator. Sampling is at higher rate at the second modulator and decimation is performed before summing its output to the output of the first modulator.

Abstract translation: 具有1.5位的第一调制器和1位的第二调制器的连续时间MASHΣ-ΔADC也接收来自另一个调制器的反馈。 在第二调制器处采样速率较高，并且在将其输出与第一调制器的输出相加之前进行抽取。

公开(公告)号：US09094040B2

公开(公告)日：2015-07-28

申请号：US14368040

申请日：2012-12-29

Applicant: ST-Ericsson SA

Inventor： Kimmo Koli

IPC: H03M3/00 ,  H03M1/06

CPC classification number: H03M3/462 ,  H03M1/06 ,  H03M3/394 ,  H03M3/414 ,  H03M3/436 ,  H03M3/496

Abstract: A continuous-time MASH sigma-delta analogue-to-digital converter ADC. The ADC may include first and second modulators and an output stage. The ADC may be provided with a first modulator with 1.5 bit and a second modulator with 1 bit each receiving also the feedback from the other modulator. Sampling is at higher rate at the second modulator and decimation is performed before summing its output to the output of the first modulator.

Abstract translation: 连续时间的MASHΣ-Δ模数转换器ADC。 ADC可以包括第一和第二调制器和输出级。 ADC可以设置有具有1.5位的第一调制器和具有1位的第二调制器，每个还接收来自另一个调制器的反馈。 在第二调制器处采样速率较高，并且在将其输出与第一调制器的输出相加之前进行抽取。

公开(公告)号：US09491015B2

公开(公告)日：2016-11-08

申请号：US14892739

申请日：2014-06-17

Applicant: ST-Ericsson SA

Inventor： Kimmo Koli

IPC: H04L7/00 ,  H04L25/49 ,  H04L25/02 ,  H04B7/06

CPC classification number: H04L25/4917 ,  H04B7/06 ,  H04L7/0079 ,  H04L25/0272 ,  H04L25/0292

Abstract: A receiver for a three-wire digital interface, a method for operating a three-wire digital interface, a signalling system comprising the receiver, and a wireless communication device comprising the signalling system. The receiver for a three-wire digital interface comprises a first resistive element coupled between a first input terminal and a first junction node, a second resistive element coupled between a second input terminal and a second junction node, and a third resistive element coupled between a third input terminal and a third junction node. A network comprising first second and third network terminals is coupled to first, second and third junction nodes. The network has substantially the same impedance between all pairs of the first, second and third network terminals.

Abstract translation: 用于三线数字接口的接收机，用于操作三线数字接口的方法，包括接收机的信令系统以及包括信令系统的无线通信设备。 用于三线数字接口的接收机包括耦合在第一输入端和第一结节之间的第一电阻元件，耦合在第二输入端与第二结节之间的第二电阻元件， 第三输入端和第三结节点。 包括第一和第三网络终端的网络耦合到第一，第二和第三连接节点。 网络在第一，第二和第三网络终端的所有对之间具有基本上相同的阻抗。

公开(公告)号：US09191127B2

公开(公告)日：2015-11-17

申请号：US14363954

申请日：2012-12-20

Applicant: ST-Ericsson SA

Inventor： Kimmo Koli

IPC: H04B1/10 ,  H04B15/00 ,  H03H19/00 ,  H04B1/40 ,  H04W84/12

CPC classification number: H04B15/00 ,  H03H19/008 ,  H04B1/40 ,  H04W84/12

Abstract: A signal filter (100) comprises a first transferred impedance filter, TIF, (TIFA) having four differential signal paths (PA,1, PA,2, PA,3, PA,4) and a second TIF (TIFB) having four differential signal paths (PB,1, PB,2, PB,3, PB,4)- A first differential signal port of the first TIF (32A) is coupled to a first differential signal port of the second TIF (32B). A first clock generator (12A) is arranged to provide first-TIF clock signals (CLKA,I+, CLKA,Q+, CLKA,I−, CLKA,Q−) having four non-overlapping phases for selecting the respective first-TIF differential signal paths (PA,1, PA,2, PA,3, PA,4), and a second clock generator (12B) is arranged to provide second-TIF clock signals (CLKB,I+, CLKB,Q+, CLKB,J−, CLKB,Q−) having four non-overlapping phases for selecting the respective second-TIF differential signal paths (PB,1, PB,2, PB,3, PB,4). The phases of the second-TIF clock signals (CLKB,I+, CLKB,Q+, CLKB,I−, CLKB,Q−) are equal to the phases of the first-TIF clock signals (CLKA,I+, CLKA,Q+, CLKA,I−, CLKA,Q−) delayed by 45 degrees. The first-TIF first, second, third and fourth clock signals (CLKA,I+, CLKA,Q+, CLKA,I−, CLKAQ−) and the second-TIF first, second, third and fourth clock signals (CLKB,I+, CLKB,Q+, CLKB,I−, CLKB,Q−) have a duty cycle in the range 16.75% to 25%.

Abstract translation: 信号滤波器（100）包括具有四个差分信号路径（PA，1，PA，2，PA，3，PA，4）和具有四个差分信号的第二TIF（TIFB）的第一传输阻抗滤波器TIF（TIFA） 信号路径（PB，1，PB，2，PB，3，PB，4） - 第一TIF（32A）的第一差分信号端口耦合到第二TIF（32B）的第一差分信号端口。 第一时钟发生器（12A）被布置成提供具有四个非重叠相位的第一TIF时钟信号（CLKA，I +，CLKA，Q +，CLKA，I，CLKA，Q-），用于选择相应的第一TIF差分信号 路径（PA，1，PA，2，PA，3，PA，4）和第二时钟发生器（12B）被布置成提供第二TIF时钟信号（CLKB，I +，CLKB，Q +，CLKB，J-， CLKB，Q-）具有用于选择相应的第二TIF差分信号路径（PB，1，PB，2，PB，3，PB，4）的四个非重叠相位。 第二TIF时钟信号（CLKB，I +，CLKB，Q +，CLKB，I，CLKB，Q-）的相位等于第一TIF时钟信号（CLKA，I +，CLKA，Q +，CLKA ，I-，CLKA，Q-）延迟45度。 第一TIF第一，第二，第三和第四时钟信号（CLKA，I +，CLKA，Q +，CLKA，I，CLKAQ-）和第二TIF第一，第二，第三和第四时钟信号（CLKB，I +，CLKB ，Q +，CLKB，I，CLKB，Q-）具有16.75％至25％范围内的占空比。