公开(公告)号：US20210035952A1

公开(公告)日：2021-02-04

申请号：US16935081

申请日：2020-07-21

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yong CHEN ,  David GANI

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/16 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00

Abstract: A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.

公开(公告)号：US20230197688A1

公开(公告)日：2023-06-22

申请号：US18166931

申请日：2023-02-09

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yong CHEN ,  David GANI

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L25/16 ,  H01L23/13

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L21/565 ,  H01L21/563 ,  H01L23/49866 ,  H01L25/16 ,  H01L23/13 ,  H01L24/32 ,  H01L23/49816 ,  H01L2224/05009 ,  H01L2225/06503 ,  H01L2224/32225

Abstract: A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.

公开(公告)号：US20210066198A1

公开(公告)日：2021-03-04

申请号：US16987002

申请日：2020-08-06

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yong CHEN ,  David GANI

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: The present disclosure is directed to a package that includes openings that extend into the package. The openings are filled with a conductive material to electrically couple a first die in the package to a second die in the package. The conductive material that fills the openings forms electrical interconnection bridges between the first die and the second die. The openings in the package may be formed using a laser and a non-doped molding compound, a doped molding compound, or a combination of doped or non-doped molding compounds.

公开(公告)号：US20230230949A1

公开(公告)日：2023-07-20

申请号：US18153937

申请日：2023-01-12

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yong CHEN ,  David GANI

IPC: H01L23/00

CPC classification number: H01L24/24 ,  H01L24/16 ,  H01L24/73 ,  H01L2924/35121 ,  H01L2224/2402 ,  H01L2224/2405 ,  H01L2224/24226 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73209

Abstract: A semiconductor package includes a die and a first lamination layer on the die with openings through the first lamination layer. A redistribution layer is on the first lamination layer and extends through the openings to the die. A plurality of conductive extensions are on the redistribution layer with each stud including a first surface on the redistribution layer, a second surface opposite to the first surface, and a sidewall between the first surface and the second surface. A second lamination layer is on the redistribution layer and the first lamination layer with the die encapsulated in molding compound. The second lamination layer is removed around the conductive extensions to expose the second surface and at least a portion of the sidewall of each stud to improve solder bond strength when mounting the package to a circuit board.