公开(公告)号：US20220068395A1

公开(公告)日：2022-03-03

申请号：US17407903

申请日：2021-08-20

Applicant: STMicroelectronics S.r.l.

Inventor： Marcella CARISSIMI ,  Fabio Enrico Carlo DISEGNI ,  Chantal AURICCHIO ,  Cesare TORTI ,  Davide MANFRE' ,  Laura CAPECCHI ,  Emanuela CALVETTI ,  Stefano ZANCHI

IPC: G11C16/10 ,  G11C16/28 ,  G11C16/24 ,  G11C16/30 ,  G11C7/04

Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.

公开(公告)号：US20150003168A1

公开(公告)日：2015-01-01

申请号：US14305482

申请日：2014-06-16

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Cesare TORTI

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C7/062 ,  G11C7/065 ,  G11C7/067 ,  G11C11/5642 ,  G11C16/28

Abstract: A non-volatile memory device includes a sense amplifier for comparing a conduction current of a selected one of a plurality of memory cells with a reference current. The sense amplifier includes an amplification stage having a first input terminal for receiving a first comparison voltage, a second input terminal for receiving a reference value, and an output terminal for providing a second comparison voltage. A buffer stage has an output terminal for providing a comparison current according to a difference between the conduction current and the reference current, and an input terminal for stabilizing the first comparison voltage at the reference value and the second comparison voltage at a comparison value unbalanced with respect to the reference value according to the comparison current. A latching stage indicates a logic level stored in the memory cell according to a difference between the comparison value and the reference value.

Abstract translation: 非易失性存储器件包括读出放大器，用于将多个存储器单元中所选择的一个存储器单元的导通电流与参考电流进行比较。 读出放大器包括具有用于接收第一比较电压的第一输入端子，用于接收基准值的第二输入端子和用于提供第二比较电压的输出端子的放大级。 缓冲级具有输出端子，用于根据导通电流和参考电流之间的差异提供比较电流;以及输入端子，用于使参考值处的第一比较电压和第二比较电压以不平衡的比较值稳定， 根据比较电流对参考值的影响。 锁存级根据比较值和参考值之间的差异指示存储在存储单元中的逻辑电平。