公开(公告)号：US20230251795A1

公开(公告)日：2023-08-10

申请号：US17669085

申请日：2022-02-10

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Fabio Enrico Carlo DISEGNI ,  Federico GOLLER ,  Dario FALANGA ,  Michele FEBBRARINO ,  Massimo MONTANARO

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679

Abstract: A non-volatile memory receives a data read request from a processing core of a plurality of processing cores. The read request is directed to a data partition of a non-volatile memory. The non-volatile memory determines whether to process the read request using read-while-write collision management. When it is determined to process the read request using read-while-write collision management, an address associated with the read request is stored in an address register of a set of registers associated with the processing core. Write operations directed to the data partition are suspended. A read operation associated with the read request is executed while the write operations are suspended and data responsive to the read operation is stored in one or more data registers of the set of registers. The data stored in the one or more data registers of the set of registers is provided to the processing core.

公开(公告)号：US20230223079A1

公开(公告)日：2023-07-13

申请号：US18148378

申请日：2022-12-29

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Alessandro TOMASONI ,  Fabio Enrico Carlo DISEGNI ,  Marcella CARISSIMI ,  Daniele LO IACONO

IPC: G11C11/56 ,  G11C13/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C2013/0054

Abstract: The present disclosure is directed to a method for storing information in a coded manner in non-volatile memory cells. The method includes providing a group of non-volatile memory cells of non volatile memory. The memory cell is of the type in which a stored logic state, which can be logic high or logic low, can be changed through application of a current to the cell and the state in the memory cell is read by reading a current provided by the cell. The group of non-volatile memory cells include a determined number of non-volatile memory cells which is greater than two. The group of non-volatile memory cells store a codeword formed by the values of said stored states of the cells of the group taken according to a given order. Given a set of codewords obtainable by the stored values in the determined number of non-volatile memory cells in a group, the method includes storing the information in at least two subsets of said set of codewords comprising each at least a codeword. Each codeword in a same subset has a same Hamming weight. Each codeword belonging to one subset has a Hamming distance equal or greater than two with respect to each codeword belonging to another subset.

公开(公告)号：US20220068395A1

公开(公告)日：2022-03-03

申请号：US17407903

申请日：2021-08-20

Applicant: STMicroelectronics S.r.l.

Inventor： Marcella CARISSIMI ,  Fabio Enrico Carlo DISEGNI ,  Chantal AURICCHIO ,  Cesare TORTI ,  Davide MANFRE' ,  Laura CAPECCHI ,  Emanuela CALVETTI ,  Stefano ZANCHI

IPC: G11C16/10 ,  G11C16/28 ,  G11C16/24 ,  G11C16/30 ,  G11C7/04

Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.

公开(公告)号：US20230245699A1

公开(公告)日：2023-08-03

申请号：US18148380

申请日：2022-12-29

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Fabio Enrico Carlo DISEGNI ,  Marcella CARISSIMI ,  Alessandro TOMASONI ,  Daniele LO IACONO

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C2013/0045 ,  G11C2013/0054

Abstract: The present disclosure is directed to a sense amplifier architecture for a memory device having a plurality of memory cells. Groups of non-volatile memory cells store respective codewords formed by stored logic states, logic high or logic low, of the memory cells of the group. The sense amplifier architecture has a plurality of sense amplifier reading branches, each sense amplifier reading branch coupled to a respective memory cell and configured to provide an output signal, which is indicative of a cell current flowing through the same memory cell; a comparison stage, to perform a comparison between the cell currents of memory cells of a group; and a logic stage, to determine, based on comparison results provided by the comparison stage, a read codeword corresponding to the group of memory cells. Information may be stored in different subsets of codewords, the sense amplifier architecture in this case having a subset definition circuit, to allow a preliminary determination of the subset to which a codeword to be read belongs to, based on reference signals.

公开(公告)号：US20230168300A1

公开(公告)日：2023-06-01

申请号：US18053688

申请日：2022-11-08

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Mauro GIACOMINI ,  Fabio Enrico Carlo DISEGNI ,  Rajesh NARWAL ,  Pravesh Kumar SAINI ,  Mayankkumar HARESHBHAI NIRANJANI

IPC: G01R31/315 ,  H01L21/66

CPC classification number: G01R31/315 ,  H01L22/12

Abstract: An assembly for detecting a structural defect in a semiconductor die is provided. The assembly includes a defect-detection sensor and a microcontroller. The defect-detection sensor includes a plurality of resistive paths of electrical-conductive material in the semiconductor die, each of which has a first end and a second end and extends proximate a perimeter of the semiconductor die. The defect-detection sensor includes a plurality of signal-generation structures, each coupled to a respective resistive path and configured to supply a test signal to the resistive path. The microcontroller is configured to control the signal-generation structures to generate the test signals, acquire the test signals in each resistive paths, test an electrical feature of the resistive paths by performing an analysis of the test signals acquired and detect the presence of the structural defect in the semiconductor die based on a result of the analysis of the test signals acquired.

公开(公告)号：US20170147416A1

公开(公告)日：2017-05-25

申请号：US14951639

申请日：2015-11-25

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Om RANJAN ,  Fabio Enrico Carlo DISEGNI

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/08 ,  G06F11/1004 ,  G06F11/16 ,  G11B2020/1843 ,  G11C29/02 ,  G11C29/04 ,  G11C29/42

Abstract: An electronic device includes a memory having memory locations being subject to transient faults and permanent faults, and a fault detection circuit coupled to the memory. The fault detection circuit is configured to read the memory locations at a first time, and determine a first fault count and fault map signature including the transient and permanent faults at the first time based upon reading the plurality of memory locations, and to store the first fault count and fault map signature. The fault detection circuit is configured to read the memory locations at a second time and determine a second fault count and fault map signature including the transient and permanent faults at the second time based upon reading the memory locations, and compare the stored first fault count and fault map signature with the second fault count and fault map signature to determine a permanent fault count.