公开(公告)号：US20240006277A1

公开(公告)日：2024-01-04

申请号：US18369652

申请日：2023-09-18

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto ARRIGONI ,  Giovanni GRAZIOSI ,  Aurora SANNA

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49589 ,  H01L21/4825 ,  H01L23/49503 ,  H01L23/4952

Abstract: Disclosed herein is a method for manufacturing a semiconductor product package. The method includes arranging a leadframe with one or more leads such that each lead has an inner end facing a portion of a die-pad, attaching a semiconductor chip to the die-pad, attaching a first electrically conductive mass to the die-pad such that it is aligned with the inner end of a lead protruding over the die-pad, attaching an electrical component to the first electrically conductive mass such that a longitudinal axis of the electrical component is arranged traverse to the die-pad, and coupling a second electrically conductive mass between a termination of the electrical component and the inner end of the lead.

公开(公告)号：US20190148282A1

公开(公告)日：2019-05-16

申请号：US16245549

申请日：2019-01-11

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio FONTANA ,  Giovanni GRAZIOSI

IPC: H01L23/498 ,  H01L21/52 ,  H01L23/367 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

Abstract: A method for forming an electronic device includes embedding an integrated circuit die in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.

公开(公告)号：US20200235045A1

公开(公告)日：2020-07-23

申请号：US16745043

申请日：2020-01-16

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto ARRIGONI ,  Giovanni GRAZIOSI ,  Aurora SANNA

IPC: H01L23/495 ,  H01L21/48

Abstract: A semiconductor chip is mounted to a chip mounting portion of a leadframe which further includes and one or more leads in the leadframe arranged facing the chip mounting portion. The lead lies in a first plane and the chip mounting portion lies in a second plane, the first plane and the second plane mutually offset with a gap therebetween. An electrical component (such as a capacitor) is arranged on the chip mounting portion and extends vertically between the first plane and the second plane.

公开(公告)号：US20190259691A1

公开(公告)日：2019-08-22

申请号：US16398022

申请日：2019-04-29

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fulvio Vittorio FONTANA ,  Giovanni GRAZIOSI

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L49/02

Abstract: In an embodiment, a semiconductor device includes: a lead-frame including one or more electrically conductive areas, one or more dielectric layers over the electrically conductive area or areas, one or more electrically conductive layer over the one or more dielectric layers thus forming one or more capacitors each including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer. The semiconductor device also includes a semiconductor die on the lead-frame electrically connected to the one or more electrically conductive layers.

公开(公告)号：US20240413120A1

公开(公告)日：2024-12-12

申请号：US18808330

申请日：2024-08-19

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni GRAZIOSI ,  Michele DERAI

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/495 ,  H01L23/64

Abstract: Disclosed herein is a method, including attaching a semiconductor chip to a chip mounting portion on at least one leadframe portion, and attaching a passive component on a passive component mounting portion of the at least one leadframe portion. The method further includes forming a laser direct structuring (LDS) activatable molding material over the semiconductor chip, passive component, and the at least one leadframe portion. Desired patterns of structured areas are formed within the LDS activatable molding material by activating the LDS activatable molding material. The desired patterns of structured areas are metallized to form conductive areas within the LDS activatable molding material to thereby form electrical connection between the semiconductor chip and the passive component. A passivation layer is formed on the LDS activatable molding material.

公开(公告)号：US20210305203A1

公开(公告)日：2021-09-30

申请号：US17344149

申请日：2021-06-10

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni GRAZIOSI ,  Michele DERAI

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/64 ,  H01L23/29 ,  H01L23/31

Abstract: Disclosed herein is a method, including attaching a semiconductor chip to a chip mounting portion on at least one leadframe portion, and attaching a passive component on a passive component mounting portion of the at least one leadframe portion. The method further includes forming a laser direct structuring (LDS) activatable molding material over the semiconductor chip, passive component, and the at least one leadframe portion. Desired patterns of structured areas are formed within the LDS activatable molding material by activating the LDS activatable molding material. The desired patterns of structured areas are metallized to form conductive areas within the LDS activatable molding material to thereby form electrical connection between the semiconductor chip and the passive component. A passivation layer is formed on the LDS activatable molding material.

公开(公告)号：US20230005803A1

公开(公告)日：2023-01-05

申请号：US17847824

申请日：2022-06-23

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni GRAZIOSI ,  Michele DERAI

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/29

Abstract: A semiconductor chip is arranged on a first surface of a die pad in a substrate (leadframe) including an array of electrically conductive leads. An encapsulation of laser direct structuring (LDS) material encapsulates the substrate and the semiconductor chip. The encapsulation has a first surface, a second surface opposed to the first surface and a peripheral surface. The array of electrically conductive leads protrude from the peripheral surface with areas of the second surface of the encapsulation arranged between adjacent leads. LDS structured areas of the second surface located between adjacent leads in the array of electrically conductive leads provide a further array of electrically conductive leads exposed at the second surface. First and second electrically conductive vias extending through the encapsulation material as well as electrically conductive lines over the encapsulation material provide an electrical bonding pattern between the semiconductor chip and selected ones of the leads.

公开(公告)号：US20220238405A1

公开(公告)日：2022-07-28

申请号：US17573339

申请日：2022-01-11

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni GRAZIOSI ,  Aurora SANNA ,  Riccardo VILLA

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/66 ,  H01Q1/22

Abstract: An antenna-in-package semiconductor device includes a semiconductor chip coupled to a planar substrate. An encapsulation body encapsulates the semiconductor chip. The encapsulation body includes a through cavity extending to the planar substrate. A rectilinear wire antenna is mounted within the through cavity and extends, for instance from the planar substrate, along an axis that is transverse to a surface of the planar substrate to which the semiconductor chip is coupled. The rectilinear wire antenna is electrically coupled to the semiconductor chip. An insulating material fills the cavity to encapsulated the rectilinear wire antenna.

公开(公告)号：US20210407894A1

公开(公告)日：2021-12-30

申请号：US17470269

申请日：2021-09-09

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Fulvio Vittorio FONTANA ,  Giovanni GRAZIOSI ,  Michele DERAI

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

Abstract: Methods of forming a semiconductor device comprising a lead-frame having a die pad having at least one electrically conductive die pad area and an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.

公开(公告)号：US20210167029A1

公开(公告)日：2021-06-03

申请号：US17108694

申请日：2020-12-01

Applicant: STMicroelectronics S.r.l.

Inventor： Cristina SOMMA ,  Giovanni GRAZIOSI

IPC: H01L23/00 ,  H01L27/02 ,  H01L23/13 ,  H01L23/14

Abstract: A first device includes a rectangular substrate having a first width and a first length and a first pattern of electrical interface nodes at first, second and third sides with a first set of electrical interface nodes at the fourth side. A second device includes a second rectangular substrate having a second width equal to the first width, a second length and a median line extending in the direction of the second width. A second pattern of electrical interface nodes for the second device includes two unmorphed replicas of the first pattern arranged mutually rotated 180° on opposite sides of the median line as well as two second sets of electrical interface nodes formed by two smaller morphed replicas of the first set of electrical interface nodes arranged mutually rotated 180° on opposite sides of said median line.