公开(公告)号：US20200098760A1

公开(公告)日：2020-03-26

申请号：US16697103

申请日：2019-11-26

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre MORIN ,  Nicolas LOUBET

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

公开(公告)号：US20170084733A1

公开(公告)日：2017-03-23

申请号：US15365640

申请日：2016-11-30

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas LOUBET ,  Pierre MORIN

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/49 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7849 ,  H01L2029/7858

Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.

公开(公告)号：US20160172497A1

公开(公告)日：2016-06-16

申请号：US14975534

申请日：2015-12-18

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas LOUBET ,  Pierre MORIN

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/165 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

公开(公告)号：US20210050449A1

公开(公告)日：2021-02-18

申请号：US17087218

申请日：2020-11-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre MORIN ,  Nicolas LOUBET

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L27/088

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

公开(公告)号：US20180158945A1

公开(公告)日：2018-06-07

申请号：US15884843

申请日：2018-01-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre MORIN ,  Nicolas LOUBET

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L27/088 ,  H01L29/417 ,  H01L29/161 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7849 ,  H01L2029/7858

Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.

公开(公告)号：US20150140760A1

公开(公告)日：2015-05-21

申请号：US14597457

申请日：2015-01-15

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas LOUBET ,  Pierre Morin

IPC: H01L29/15 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Abstract translation: 描述形成应变通道鳍状FET的方法和结构。 用于finFET的鳍结构可以形成在生长在块状衬底上的两个外延层中。 可以将第一薄外延层切割并用于通过弹性弛豫向finFET的相邻沟道区施加应变。 该结构表现出优选的设计范围，用于增加应变在翅片高度上的诱导应变和均匀性。

公开(公告)号：US20150108585A1

公开(公告)日：2015-04-23

申请号：US14587872

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas LOUBET ,  Prasanna KHARE

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L29/16

CPC classification number: H01L29/0653 ,  H01L21/02532 ,  H01L21/02661 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/7848

Abstract: Channel-to-substrate leakage in a FinFET device can be prevented by inserting an insulating layer between the semiconducting channel and the substrate. Similarly, source/drain-to-substrate leakage in a FinFET device can be prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. The insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. If an array of semiconducting fins is made up of a multi-layer stack, the bottom material can be removed thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material can then be filled in with oxide to better support the fins and to isolate the array of fins from the substrate. The resulting FinFET device is fully substrate-isolated in both the gate region and the source/drain regions.

Abstract translation: 可以通过在半导体沟道和衬底之间插入绝缘层来防止FinFET器件中的沟道对衬底的泄漏。 类似地，通过在源极/漏极区域和衬底之间插入绝缘层，可以防止FinFET器件中的源极/漏极到衬底的泄漏。 绝缘层在物理和电气上隔离了基板的导电路径，从而防止电流泄漏。 如果半导体翅片的阵列由多层堆叠构成，则可以去除底部材料，从而产生悬浮在硅表面上方的翅片阵列。 然后可以用氧化物填充剩下的顶部翅片材料之下的产生的间隙，以更好地支撑翅片并将翅片阵列与基底隔离开。 所得到的FinFET器件在栅极区域和源极/漏极区域中完全衬底隔离。

公开(公告)号：US20250126850A1

公开(公告)日：2025-04-17

申请号：US19000478

申请日：2024-12-23

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas LOUBET ,  Pierre MORIN

IPC: H10D30/69 ,  H10D30/01 ,  H10D30/62 ,  H10D62/815 ,  H10D62/822 ,  H10D62/83 ,  H10D62/832

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

公开(公告)号：US20180261674A1

公开(公告)日：2018-09-13

申请号：US15979326

申请日：2018-05-14

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas LOUBET ,  Prasanna KHARE

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L29/41791 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer is used to define a plurality of fins in the semiconductor layer. A gate is formed over the plurality of fins.

公开(公告)号：US20170263495A1

公开(公告)日：2017-09-14

申请号：US15457447

申请日：2017-03-13

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS Inc

Inventor： Emmanuel AUGENDRE ,  Nicolas LOUBET ,  Sylvain MAITREJEAN ,  Pierre MORIN

IPC: H01L21/762 ,  H01L29/16 ,  H01L29/78

Abstract: The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps: a) providing a substrate coated with a masking layer wherein there are one or several first slits exposing one or several first oblong semiconducting portions made of a first semiconducting material and extending in a first direction, b) making a second semiconducting material grow with a mesh parameter different from the mesh parameter of the first semiconducting material, so as to form one or several first semiconducting blocks strained along the first direction, on said one or several first oblong semiconducting portions.