公开(公告)号：US11043591B2

公开(公告)日：2021-06-22

申请号：US16437067

申请日：2019-06-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mickael Gros-Jean ,  Julien Ferrand

IPC: H01L29/78 ,  H01L27/07 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

Abstract: A ferroelectric field effect transistor includes a semiconductor substrate, with first and second source/drain regions being formed within the semiconductor substrate and being separated by a channel region. An interface layer is disposed on the channel region. A gate insulator layer is disposed on the interface layer. A ferroelectric layer is disposed on the gate insulator layer.

公开(公告)号：US11677024B2

公开(公告)日：2023-06-13

申请号：US17323545

申请日：2021-05-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mickael Gros-Jean ,  Julien Ferrand

IPC: H01L29/78 ,  H01L21/28 ,  H01L27/07 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L27/0705 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684

Abstract: A method for manufacturing first and second transistors on a semiconductor substrate includes: depositing an interface layer on the semiconductor substrate; depositing a gate insulator layer on the interface layer; depositing a first ferroelectric layer on the gate insulator layer over a first region for the first transistor; depositing a metal gate layer on the gate insulator layer over a second region for the second transistor and on the first ferroelectric layer over the first region for the first transistor; and patterning the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer to form a first gate stack for the first transistor which includes the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer and a second gate stack for the second transistor which includes the metal gate layer, gate insulator layer and interface layer.