公开(公告)号：US20240081160A1

公开(公告)日：2024-03-07

申请号：US18506383

申请日：2023-11-10

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN ,  Simon JEANNOT

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/061 ,  H10N70/253 ,  H10N70/823 ,  H10N70/826 ,  H10N70/8265 ,  H10N70/8413 ,  H10N70/8828 ,  G11C13/0004

Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

公开(公告)号：US20190214434A1

公开(公告)日：2019-07-11

申请号：US16357152

申请日：2019-03-18

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN ,  Simon JEANNOT

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  G11C13/0004 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1666

Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

公开(公告)号：US20180233511A1

公开(公告)日：2018-08-16

申请号：US15954874

申请日：2018-04-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto PIAZZA ,  Sebastien LAGRASTA ,  Raul Andres BIANCHI ,  Simon JEANNOT

IPC: H01L27/11546 ,  H01L29/66 ,  H01L21/02 ,  H01L29/49 ,  H01L49/02 ,  H01L27/11521 ,  H01L27/06 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/11541

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

公开(公告)号：US20210280779A1

公开(公告)日：2021-09-09

申请号：US17328917

申请日：2021-05-24

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN ,  Simon JEANNOT

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

公开(公告)号：US20210057426A1

公开(公告)日：2021-02-25

申请号：US17092551

申请日：2020-11-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto PIAZZA ,  Sebastien LAGRASTA ,  Raul Andres BIANCHI ,  Simon JEANNOT

IPC: H01L27/11546 ,  H01L21/28 ,  H01L27/06 ,  H01L49/02 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11521 ,  H01L29/49 ,  H01L29/66

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

公开(公告)号：US20190326510A1

公开(公告)日：2019-10-24

申请号：US16457855

申请日：2019-06-28

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN ,  Simon JEANNOT

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.