Voltage Converter
    1.
    发明申请

    公开(公告)号:US20210135574A1

    公开(公告)日:2021-05-06

    申请号:US17089102

    申请日:2020-11-04

    Abstract: In an embodiment, a voltage converter includes: a first transistor coupled between an internal node and a first node receiving a supply voltage; a second transistor coupled between the internal node and a second node receiving a reference voltage; an inductance coupled between the internal node and an output node; a first circuit controlling the first and second transistors; and a second circuit configured to detect, when the first and second transistors are in the off state, when the voltage of the internal node is equal to the voltage of the output node, to condition a switching to the on state of the first transistor.

    DC-DC BUCK SMPS
    3.
    发明申请

    公开(公告)号:US20220360172A1

    公开(公告)日:2022-11-10

    申请号:US17661361

    申请日:2022-04-29

    Abstract: The present disclosure relates to a switched-mode Power Supply Buck Converter comprising: a switch connected between a node receiving a supply potential and an internal node; another switch connected between the internal node and a node receiving a reference potential; an inductive element coupling the internal node to an output node; and a control circuit controlling the switches so that current pulses in the inductive element have a maximum value selected from among at least a first value and a second value based on an average current drawn at the output node.

    VOLTAGE CONVERTER
    4.
    发明申请

    公开(公告)号:US20210126535A1

    公开(公告)日:2021-04-29

    申请号:US17078284

    申请日:2020-10-23

    Abstract: In an embodiment, a voltage converter includes: a first transistor coupled between a first rail configured to receive a supply voltage and a first node; and an inductance coupled between the first node and a second node configured to deliver an output voltage, wherein, at each operating cycle of the converter, the first transistor is maintained in the on state for a first time period proportional to the inverse of a voltage difference between the supply voltage and the output voltage.

    Adaptive current threshold controlled SMPS buck converter with pulse frequency modulation

    公开(公告)号:US12107499B2

    公开(公告)日:2024-10-01

    申请号:US17661361

    申请日:2022-04-29

    CPC classification number: H02M3/158

    Abstract: The present disclosure relates to a switched-mode Power Supply Buck Converter comprising: a switch connected between a node receiving a supply potential and an internal node; another switch connected between the internal node and a node receiving a reference potential; an inductive element coupling the internal node to an output node; and a control circuit controlling the switches so that current pulses in the inductive element have a maximum value selected from among at least a first value and a second value based on an average current drawn at the output node.

    DC/DC voltage converter and method

    公开(公告)号:US11616440B2

    公开(公告)日:2023-03-28

    申请号:US17089102

    申请日:2020-11-04

    Abstract: In an embodiment, a voltage converter includes: a first transistor coupled between an internal node and a first node receiving a supply voltage; a second transistor coupled between the internal node and a second node receiving a reference voltage; an inductance coupled between the internal node and an output node; a first circuit controlling the first and second transistors; and a second circuit configured to detect, when the first and second transistors are in the off state, when the voltage of the internal node is equal to the voltage of the output node, to condition a switching to the on state of the first transistor.

    Method of adjusting a pulse width modulation signal

    公开(公告)号:US11575306B2

    公开(公告)日:2023-02-07

    申请号:US17242955

    申请日:2021-04-28

    Abstract: A method for increasing performance of a voltage-buck switched-mode voltage regulator includes generating a first pulse-width modulation signal based on a clock signal, decreasing a frequency of the clock signal to form a modified clock signal, passing the modified clock signal to a digital modulation circuit as a regulated clock signal; and generating a second pulse-width modulation signal based on the regulated clock signal using the digital modulation circuit. The first pulse-width modulation signal includes a period T1 and an off duration D2 corresponding to a first duty cycle. The off duration D2 is an intrinsic pulse-width modulation signal generation latency. The second pulse-width modulation signal includes a period T2 and the off duration D2. The decreased frequency of the modified clock signal causes T2 to be greater than T1 such that a second duty cycle of the second pulse-width modulation signal is increased relative to the first duty cycle.

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