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公开(公告)号：US20190118544A1
公开(公告)日：2019-04-25
申请号：US16220476
申请日：2018-12-14
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista , Victorien Brecte
IPC: B41J2/175
CPC classification number: B41J2/17556 , B41J2/175 , B41J2/17523 , B41J2/17596 , G11C7/067 , G11C16/0433 , G11C16/24 , G11C16/26
Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.
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公开(公告)号：US09779825B2
公开(公告)日：2017-10-03
申请号：US15183515
申请日：2016-06-15
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista , Victorien Brecte
CPC classification number: G11C16/26 , G11C7/067 , G11C16/0433 , G11C16/24
Abstract: One embodiment provides a method for reading a memory cell of a memory plane of a memory of the erasable electrically-programmable ROM type. The word line and of the bit line to which the memory cell belongs are selected and the content of the cell is read via a read amplifier. One input of the read amplifier is connected to the bit line and pre-charged at a pre-charge voltage. During the read operation, a source voltage higher than the pre-charge voltage is applied to the source of the floating-gate transistor of the cell. A read current flows from the cell towards the input of the read amplifier and then flows through a programmed cell.
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公开(公告)号：US09761316B2
公开(公告)日：2017-09-12
申请号：US15141084
申请日：2016-04-28
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Victorien Brecte
Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.
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公开(公告)号：US20170125112A1
公开(公告)日：2017-05-04
申请号：US15183515
申请日：2016-06-15
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista , Victorien Brecte
CPC classification number: G11C16/26 , G11C7/067 , G11C16/0433 , G11C16/24
Abstract: One embodiment provides a method for reading a memory cell of a memory plane of a memory of the erasable electrically-programmable ROM type. The word line and of the bit line to which the memory cell belongs are selected and the content of the cell is read via a read amplifier. One input of the read amplifier is connected to the bit line and pre-charged at a pre-charge voltage. During the read operation, a source voltage higher than the pre-charge voltage is applied to the source of the floating-gate transistor of the cell. A read current flows from the cell towards the input of the read amplifier and then flows through a programmed cell.
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公开(公告)号：US10186320B2
公开(公告)日：2019-01-22
申请号：US15659891
申请日：2017-07-26
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista , Victorien Brecte
Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.
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Patent Agency Ranking
公开(公告)号：US20170323684A1
公开(公告)日：2017-11-09
申请号：US15659891
申请日：2017-07-26
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista , Victorien Brecte
CPC classification number: G11C16/26 , G11C7/067 , G11C16/0433 , G11C16/24
Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.
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公开(公告)号：US20170323683A1
公开(公告)日：2017-11-09
申请号：US15657492
申请日：2017-07-24
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Victorien Brecte
Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.
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公开(公告)号：US10675881B2
公开(公告)日：2020-06-09
申请号：US16220476
申请日：2018-12-14
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista , Victorien Brecte
Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.
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公开(公告)号：US10049753B2
公开(公告)日：2018-08-14
申请号：US15657492
申请日：2017-07-24
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Victorien Brecte
Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.
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公开(公告)号：US20170154683A1
公开(公告)日：2017-06-01
申请号：US15141084
申请日：2016-04-28
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Victorien Brecte
Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.
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