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公开(公告)号：US11303271B2
公开(公告)日：2022-04-12
申请号：US16991126
申请日：2020-08-12
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： Hong Wu Lin
Abstract: A filtering circuit for filtering a pulse width modulated (PWM) signal includes a D flip-flop having an input terminal configured to be coupled to a logic high signal and having an output terminal coupled to an output terminal of the filtering circuit; and a circuit coupled between an input terminal of the filtering circuit and the D flip-flop, the circuit configured to, for a first pulse of the PWM signal having a duty cycle within a pre-determined range: generate a positive pulse at a clock terminal of the D flip-flop as a clock signal of the D flip-flop; and generate a negative pulse at a reset terminal of the D flip-flop as a reset signal of the D flip-flop, wherein a duration between a rising edge of the positive pulse and a falling edge of the negative pulse is equal to a duration of the first pulse of the PWM signal.
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公开(公告)号：US11463052B2
公开(公告)日：2022-10-04
申请号：US17107269
申请日：2020-11-30
Inventor： Hong Wu Lin , Giovanni Gonano , Edoardo Botti
IPC: H03F3/217 , H03K17/687 , H03K19/20 , H04R3/00
Abstract: In an embodiment, a method for shaping a PWM signal includes: receiving an input PWM signal; generating an output PWM signal based on the input PWM signal by: when the input PWM signal transitions with a first edge of the input PWM signal, transitioning the output PWM signal with a first edge of the output PWM signal; and when the input PWM signal transitions with a second edge before the first edge of the output PWM signal transitions, delaying a second edge of the output PWM signal based on the first edge of the output PWM signal.
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公开(公告)号：US09525385B2
公开(公告)日：2016-12-20
申请号：US14534727
申请日：2014-11-06
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd
Inventor： Hong Wu Lin
CPC classification number: H03F1/3205 , H03F3/185 , H03F3/2171 , H03F3/2173 , H03F2200/03 , H03F2200/351 , H03F2200/66
Abstract: Limiting clipping in an amplifier is accomplished in the feedback loop of a class D PWM amplifier that includes an integrator coupled to an input node and configured to generate an integrated input signal such that a comparator may then generate a PWM signal for driving an amplifier output stage based on a comparison to a triangle wave signal. To this end, the amplifier also includes a threshold signal generator for generating high and low voltage thresholds based on the triangle wave signal to be used to engage compensation circuits for limiting the overall amplification. Such compensation circuits may be bipolar junction transistors that are disposed in the feedback loop of the integrator. Thus, the overall bandwidth of the amplifier itself is not affected by adding a limiter circuit aimed at reducing clipping.
Abstract translation: 在D类PWM放大器的反馈回路中实现限幅放大器的削波，其包括耦合到输入节点并被配置为产生积分输入信号的积分器，使得比较器然后可以产生用于驱动放大器输出级的PWM信号 基于与三角波信号的比较。 为此，放大器还包括一个阈值信号发生器，用于基于三角波信号产生高和低电压阈值，以用于接合用于限制整个放大的补偿电路。 这种补偿电路可以是布置在积分器的反馈回路中的双极结型晶体管。 因此，放大器本身的总体带宽不受增加限制电路的影响，目的是减少削波。
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公开(公告)号：US20190049511A1
公开(公告)日：2019-02-14
申请号：US16057089
申请日：2018-08-07
Inventor： Edoardo Botti , Davide Luigi Brambilla , Hong Wu Lin
IPC: G01R31/26 , H03K17/687 , G01R19/00
Abstract: A circuit includes a field effect transistor having a gate driven via a drive signal. The field effect transistor has a drain-source voltage drop indicative of the intensity of a current flowing in the current path through the field effect transistor. The circuit also includes a pair of sensing transistors that include a first sensing field effect transistor arranged with its drain and gate coupled with the drain and the gate of the field effect transistor, respectively, and a second sensing field effect transistor having a gate configured for receiving a replica of the drive signal. The second sensing field effect transistor is arranged with its current path in series with the current path of the first sensing field effect transistor. A sensing signal at a sensing node is indicative of the current intensity flowing in the current path of the field effect transistor.
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公开(公告)号：US20160329868A1
公开(公告)日：2016-11-10
申请号：US14715879
申请日：2015-05-19
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd
Inventor： Qi Yu Liu , Hong Wu Lin
CPC classification number: H03F3/183 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/45475 , H03F2200/03 , H03F2203/45138
Abstract: A class-D amplifier includes a signal processing block. The signal processing block generates a first processed signal representing a difference between a first differential signal and a second differential signal, when a duty cycle of the first differential signal is greater than that of the second differential signal. The signal processing block generates the first processed signal representing a reference DC level, when the duty cycle of the first differential signal is less than that of the second differential signal. A second processed signal representing a difference between the second differential signal and the first differential signal is generated when the duty cycle of the second differential signal is greater than that of the first differential signal, and the second processed signal representing the reference DC level is generated when the duty cycle of the second differential signal is less than that of the first differential signal.
Abstract translation: D类放大器包括信号处理块。 当第一差分信号的占空比大于第二差分信号的占空比时，信号处理块产生表示第一差分信号和第二差分信号之间的差的第一处理信号。 当第一差分信号的占空比小于第二差分信号的占空比时，信号处理块产生表示参考DC电平的第一处理信号。 当第二差分信号的占空比大于第一差分信号的占空比时，产生表示第二差分信号和第一差分信号之间的差的第二处理信号，并且生成表示参考DC电平的第二处理信号 当第二差分信号的占空比小于第一差分信号的占空比时。
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Patent Agency Ranking
公开(公告)号：US20150214902A1
公开(公告)日：2015-07-30
申请号：US14534727
申请日：2014-11-06
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd
Inventor： Hong Wu Lin
CPC classification number: H03F1/3205 , H03F3/185 , H03F3/2171 , H03F3/2173 , H03F2200/03 , H03F2200/351 , H03F2200/66
Abstract: Limiting clipping in an amplifier is accomplished in the feedback loop of a class D PWM amplifier that includes an integrator coupled to an input node and configured to generate an integrated input signal such that a comparator may then generate a PWM signal for driving an amplifier output stage based on a comparison to a triangle wave signal. To this end, the amplifier also includes a threshold signal generator for generating high and low voltage thresholds based on the triangle wave signal to be used to engage compensation circuits for limiting the overall amplification. Such compensation circuits may be bipolar junction transistors that are disposed in the feedback loop of the integrator. Thus, the overall bandwidth of the amplifier itself is not affected by adding a limiter circuit aimed at reducing clipping.
Abstract translation: 在D类PWM放大器的反馈回路中实现限幅放大器的削波，其包括耦合到输入节点并被配置为产生积分输入信号的积分器，使得比较器然后可以产生用于驱动放大器输出级的PWM信号 基于与三角波信号的比较。 为此，放大器还包括一个阈值信号发生器，用于基于三角波信号产生高和低电压阈值，以用于接合用于限制整个放大的补偿电路。 这种补偿电路可以是布置在积分器的反馈回路中的双极结型晶体管。 因此，放大器本身的总体带宽不受增加限制电路的影响，目的是减少削波。
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公开(公告)号：US20220173706A1
公开(公告)日：2022-06-02
申请号：US17107269
申请日：2020-11-30
Inventor： Hong Wu Lin , Giovanni Gonano , Edoardo Botti
IPC: H03F3/217 , H03K17/687 , H04R3/00
Abstract: In an embodiment, a method for shaping a PWM signal includes: receiving an input PWM signal; generating an output PWM signal based on the input PWM signal by: when the input PWM signal transitions with a first edge of the input PWM signal, transitioning the output PWM signal with a first edge of the output PWM signal; and when the input PWM signal transitions with a second edge before the first edge of the output PWM signal transitions, delaying a second edge of the output PWM signal based on the first edge of the output PWM signal.
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公开(公告)号：US10935592B2
公开(公告)日：2021-03-02
申请号：US16057089
申请日：2018-08-07
Inventor： Edoardo Botti , Davide Luigi Brambilla , Hong Wu Lin
IPC: G01R31/26 , H03K17/0814 , G05F3/08 , G01R19/00 , H03K17/687
Abstract: A circuit includes a field effect transistor having a gate driven via a drive signal. The field effect transistor has a drain-source voltage drop indicative of the intensity of a current flowing in the current path through the field effect transistor. The circuit also includes a pair of sensing transistors that include a first sensing field effect transistor arranged with its drain and gate coupled with the drain and the gate of the field effect transistor, respectively, and a second sensing field effect transistor having a gate configured for receiving a replica of the drive signal. The second sensing field effect transistor is arranged with its current path in series with the current path of the first sensing field effect transistor. A sensing signal at a sensing node is indicative of the current intensity flowing in the current path of the field effect transistor.
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公开(公告)号：US10749515B1
公开(公告)日：2020-08-18
申请号：US16669154
申请日：2019-10-30
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： Hong Wu Lin
Abstract: A filtering circuit for filtering a pulse width modulated (PWM) signal includes a D flip-flop having an input terminal configured to be coupled to a logic high signal and having an output terminal coupled to an output terminal of the filtering circuit; and a circuit coupled between an input terminal of the filtering circuit and the D flip-flop, the circuit configured to, for a first pulse of the PWM signal having a duty cycle within a pre-determined range: generate a positive pulse at a clock terminal of the D flip-flop as a clock signal of the D flip-flop; and generate a negative pulse at a reset terminal of the D flip-flop as a reset signal of the D flip-flop, wherein a duration between a rising edge of the positive pulse and a falling edge of the negative pulse is equal to a duration of the first pulse of the PWM signal.
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公开(公告)号：US09866187B2
公开(公告)日：2018-01-09
申请号：US14715879
申请日：2015-05-19
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd
Inventor： Qi Yu Liu , Hong Wu Lin
CPC classification number: H03F3/183 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/45475 , H03F2200/03 , H03F2203/45138
Abstract: A class-D amplifier includes a signal processing block. The signal processing block generates a first processed signal representing a difference between a first differential signal and a second differential signal, when a duty cycle of the first differential signal is greater than that of the second differential signal. The signal processing block generates the first processed signal representing a reference DC level, when the duty cycle of the first differential signal is less than that of the second differential signal. A second processed signal representing a difference between the second differential signal and the first differential signal is generated when the duty cycle of the second differential signal is greater than that of the first differential signal, and the second processed signal representing the reference DC level is generated when the duty cycle of the second differential signal is less than that of the first differential signal.
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