公开(公告)号：US20180013389A1

公开(公告)日：2018-01-11

申请号：US15713145

申请日：2017-09-22

Applicant: STMicroelectronics International N.V.

Inventor： Vinod KUMAR

IPC: H03F1/02 ,  H03K17/687 ,  H01L29/786 ,  H01L21/84 ,  H01L29/94 ,  G05F3/16 ,  H01L29/78 ,  H01L29/66 ,  H03L7/093 ,  H03F3/193

CPC classification number: H03F1/0205 ,  G05F3/16 ,  H01L21/84 ,  H01L29/66181 ,  H01L29/7831 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/94 ,  H03F3/193 ,  H03F2200/451 ,  H03K17/687 ,  H03L7/093

Abstract: Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

公开(公告)号：US20130285708A1

公开(公告)日：2013-10-31

申请号：US13931343

申请日：2013-06-28

Applicant: STMicroelectronics International N.V.

Inventor： Vinod KUMAR

IPC: H03K3/02

CPC classification number: H03K3/02 ,  G11C7/1057 ,  G11C7/1069

Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.

公开(公告)号：US20160182022A1

公开(公告)日：2016-06-23

申请号：US14573129

申请日：2014-12-17

Applicant: STMicroelectronics International N.V.

Inventor： Vinod KUMAR ,  Saiyid Mohammad Irshad RIZVI

IPC: H03K3/3565

CPC classification number: H03K3/3565

Abstract: The Schmitt trigger circuit includes a signal input, a first inverter coupled to the signal input and configured to operate at a first voltage, and a second inverter coupled downstream of the first inverter and configured to operate at a second voltage lower than the first voltage. A protection device is coupled between the first inverter and the second inverter, and configured to limit a voltage input to the second inverter at the second voltage. A feedback circuit is coupled downstream of the protection device between the first inverter and the second inverter and configured to introduce hysteresis. An output circuit is coupled to the second inverter and configured to provide an output signal at the second voltage. The approach provides an architecture for 3.3V receivers designed by using 1.8V devices, without active power consumption from the I/O PAD during transition, and/or that supports CMOS standard levels for 1.8V and 3.3V receivers.

Abstract translation: 施密特触发电路包括信号输入端，耦合到信号输入并被配置为以第一电压工作的第一反相器，以及耦合在第一反相器下游的第二反相器，并被配置为在低于第一电压的第二电压下工作。 保护装置耦合在第一反相器和第二反相器之间，并且被配置为将第二反相器的电压输入限制在第二电压。 反馈电路被耦合在第一逆变器和第二逆变器之间的保护装置的下游，并被配置为引入滞后。 输出电路耦合到第二反相器并且被配置为提供处于第二电压的输出信号。 该方法为通过使用1.8V器件设计的3.3V接收器提供了架构，在转换期间没有来自I / O PAD的有功功耗，和/或支持1.8V和3.3V接收器的CMOS标准电平。

公开(公告)号：US20150280714A1

公开(公告)日：2015-10-01

申请号：US14231447

申请日：2014-03-31

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vinod KUMAR

IPC: H03K19/0185 ,  H03K3/3562

CPC classification number: H03K19/0185 ,  H03K3/35613 ,  H03K3/356165

Abstract: A level shifter circuit is configured to receive first and second complementary input signals. Each of the first and second complementary input signals have a value of either a first supply voltage or a first reference voltage. The level shifter further includes a strong latch circuit operable in response to the first and second complementary input signals to drive one of first and second output signals to a second supply voltage and includes a weak latch circuit operable to drive the other of the first and second output signals to a second reference voltage.

Abstract translation: 电平移位器电路被配置为接收第一和第二互补输入信号。 第一和第二互补输入信号中的每一个具有第一电源电压或第一参考电压的值。 电平移位器还包括强锁存电路，其可响应于第一和第二互补输入信号而工作，以将第一和第二输出信号中的一个驱动到第二电源电压，并包括可操作以驱动第一和第二输出信号中的另一个的弱锁存电路 输出信号到第二参考电压。