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公开(公告)号：US20230087074A1
公开(公告)日：2023-03-23
申请号：US17940753
申请日：2022-09-08
Applicant: STMicroelectronics S.r.I.
Inventor： Gianbattista Lo Giudice , Antonino Conte
Abstract: A method for accessing memory cells in an array of memory cells storing respective data signals, wherein memory cells in the array of memory cells have a first, resp. second, node selectively couplable to respective bitline branches in a first, resp. second, set of bitline branches, wherein the first and the second set of bitline branches provide at least one bitline capacitance configured to store a bias level of charge in response to being charged.
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公开(公告)号：US20210297074A1
公开(公告)日：2021-09-23
申请号：US17207382
申请日：2021-03-19
Inventor： Antonino Conte , Francesco Tomaiuolo , Francesco La Rosa
Abstract: An embodiment power-on-reset circuit, having a power supply input to receive a power supply voltage, generates a reset signal with a value switching upon the power supply voltage crossing a POR detection level. The power-on-reset circuit has: a PTAT stage having a left branch and a right branch and generating a current equilibrium condition between the currents circulating in the left and right branches upon the power supply voltage reaching the POR detection level; and an output stage coupled to the PTAT stage and generating the reset signal, with the value switching at the occurrence of the current equilibrium condition for the PTAT stage. The power-on-reset circuit further comprises a detection-level generation stage, coupled to the PTAT stage as a central branch thereof to define the value of the POR detection level.
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公开(公告)号：US20240429928A1
公开(公告)日：2024-12-26
申请号：US18824653
申请日：2024-09-04
Applicant: STMicroelectronics S.r.I.
Inventor： Agatino Massimo Maccarrone , Antonino Conte , Francesco Tomaiuolo , Michelangelo Pisasale , Marco Ruta
IPC: H03M1/06
Abstract: In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror comprising a first plurality of MOS transistors and a second plurality of MOS transistors, wherein ones of the second plurality of MOS transistors are coupled between adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.
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Patent Agency Ranking
公开(公告)号：US20230130268A1
公开(公告)日：2023-04-27
申请号：US17933972
申请日：2022-09-21
Applicant: STMicroelectronics S.r.I.
Inventor： Marco Ruta , Antonino Conte , Michelangelo Pisasale , Agatino Massimo Maccarrone , Francesco Tomaiuolo
Abstract: A voltage regulator receives an input voltage and produces a regulated output voltage. A first feedback network compares a feedback signal to a reference signal to assert/de-assert a first pulsed control signal when the reference signal is higher/lower than the feedback signal. A second feedback network compares the output voltage to a threshold signal to assert/de-assert a second control signal when the threshold signal is higher/lower than the output voltage. A charge pump is enabled if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage higher than the input voltage. A first pass element is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element is selectively activated when the second control signal is de-asserted.
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公开(公告)号：US12205651B2
公开(公告)日：2025-01-21
申请号：US17940753
申请日：2022-09-08
Applicant: STMicroelectronics S.r.I.
Inventor： Gianbattista Lo Giudice , Antonino Conte
Abstract: A method for accessing memory cells in an array of memory cells storing respective data signals, wherein memory cells in the array of memory cells have a first, resp. second, node selectively couplable to respective bitline branches in a first, resp. second, set of bitline branches, wherein the first and the second set of bitline branches provide at least one bitline capacitance configured to store a bias level of charge in response to being charged.
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公开(公告)号：US20230170914A1
公开(公告)日：2023-06-01
申请号：US18054333
申请日：2022-11-10
Applicant: STMicroelectronics S.r.I.
Inventor： Agatino Massimo Maccarrone , Antonino Conte , Francesco Tomaiuolo , Michelangelo Pisasale , Marco Ruta
IPC: H03M1/06
CPC classification number: H03M1/0604
Abstract: In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror that includes a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, where ones of the second plurality of MOS transistors are coupled between drains of adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.
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7.发明申请公开(公告)号：US20190206488A1
公开(公告)日：2019-07-04
申请号：US16222484
申请日：2018-12-17
Applicant: STMicroelectronics S.r.I.
Inventor： Antonino Conte
IPC: G11C13/00
Abstract: In an embodiment, a non-volatile memory device includes a memory array divided into a plurality of tiles, and a row decoder that includes main row decoding units associated to a respective group of tiles. The row decoded further includes local row decoding units, each associated to a respective tile for carrying out selection and biasing of corresponding word lines based on decoded address signals and biasing signals. Each local row decoding unit has logic-combination modules coupled to a set of word lines and include, for each word line, a pull-down stage for selecting a word line, and a pull-up stage. The pull-up stage is dynamically biased, alternatively, in a strong-biasing condition towards a tile-supply voltage when the word line is not selected, or in a weak-biasing condition when the word line is selected.
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公开(公告)号：US20230091464A1
公开(公告)日：2023-03-23
申请号：US17934102
申请日：2022-09-21
Inventor： Francesco La Rosa , Antonino Conte , Francois Maugain
IPC: G11C16/34 , H01L27/11526 , G11C16/26 , G11C16/14 , H01L27/11521
Abstract: In an embodiment a non-volatile memory device includes a memory array having a plurality of memory cells, a control unit operatively coupled to the memory array, a biasing stage controllable by the control unit and configured to apply a biasing configuration to the memory cells to perform a memory operation and a reading stage coupled to the memory array and controllable by the control unit, the reading stage configured to verify whether the memory operation has been successful based on a verify level, wherein the control unit is configured to adaptively modify a value of the verify level based on an ageing of the memory cells.
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