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公开(公告)号:US11789046B2
公开(公告)日:2023-10-17
申请号:US17407725
申请日:2021-08-20
Applicant: STMicroelectronics S.r.l.
Inventor: Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
IPC: G01R19/10 , H03M1/12 , H03M3/00 , B60R21/017
CPC classification number: G01R19/10 , B60R21/0173 , H03M1/124 , H03M3/464 , H03M3/494
Abstract: A system and method is provided for measuring a voltage drop at a node. In embodiments, a circuit includes an analog-to-digital converter, a current sink, and a controller. The input of the analog-to-digital converter and the input of the current sink is coupled to the node to be measured. A set point for the current sink is determined. The output of the analog-to-digital converter during the voltage drop is sampled. And a relative voltage drop value is computed by subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition. The current sink operating at the set point during the steady-state condition and during the voltage drop.
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公开(公告)号:US12241946B2
公开(公告)日:2025-03-04
申请号:US18335511
申请日:2023-06-15
Applicant: STMicroelectronics S.r.l.
Inventor: Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.
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公开(公告)号:US20230324475A1
公开(公告)日:2023-10-12
申请号:US18335511
申请日:2023-06-15
Applicant: STMicroelectronics S.r.l.
Inventor: Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
CPC classification number: G01R31/64 , G01R27/2605 , G01R31/006
Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.
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公开(公告)号:US20230055745A1
公开(公告)日:2023-02-23
申请号:US17407747
申请日:2021-08-20
Applicant: STMicroelectronics S.r.l.
Inventor: Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.
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公开(公告)号:US11719761B2
公开(公告)日:2023-08-08
申请号:US17407747
申请日:2021-08-20
Applicant: STMicroelectronics S.r.l.
Inventor: Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
CPC classification number: G01R31/64 , G01R27/2605 , G01R31/006
Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.
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公开(公告)号:US20230054951A1
公开(公告)日:2023-02-23
申请号:US17407725
申请日:2021-08-20
Applicant: STMicroelectronics S.r.l.
Inventor: Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
IPC: G01R19/10 , H03M1/12 , H03M3/00 , B60R21/017
Abstract: A system and method is provided for measuring a voltage drop at a node. In embodiments, a circuit includes an analog-to-digital converter, a current sink, and a controller. The input of the analog-to-digital converter and the input of the current sink is coupled to the node to be measured. A set point for the current sink is determined. The output of the analog-to-digital converter during the voltage drop is sampled. And a relative voltage drop value is computed by subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition. The current sink operating at the set point during the steady-state condition and during the voltage drop.
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