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公开(公告)号：US12241946B2
公开(公告)日：2025-03-04
申请号：US18335511
申请日：2023-06-15
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.
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公开(公告)号：US20230324475A1
公开(公告)日：2023-10-12
申请号：US18335511
申请日：2023-06-15
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
CPC classification number: G01R31/64 , G01R27/2605 , G01R31/006
Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.
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公开(公告)号：US20230055745A1
公开(公告)日：2023-02-23
申请号：US17407747
申请日：2021-08-20
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.
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公开(公告)号：US11789046B2
公开(公告)日：2023-10-17
申请号：US17407725
申请日：2021-08-20
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
IPC: G01R19/10 , H03M1/12 , H03M3/00 , B60R21/017
CPC classification number: G01R19/10 , B60R21/0173 , H03M1/124 , H03M3/464 , H03M3/494
Abstract: A system and method is provided for measuring a voltage drop at a node. In embodiments, a circuit includes an analog-to-digital converter, a current sink, and a controller. The input of the analog-to-digital converter and the input of the current sink is coupled to the node to be measured. A set point for the current sink is determined. The output of the analog-to-digital converter during the voltage drop is sampled. And a relative voltage drop value is computed by subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition. The current sink operating at the set point during the steady-state condition and during the voltage drop.
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公开(公告)号：US11563319B1
公开(公告)日：2023-01-24
申请号：US17490285
申请日：2021-09-30
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Cignoli , Nicola Errico , Paolo Vilmercati , Stefano Castorina , Enrico Ferrara
Abstract: Disclosed herein is a single integrated circuit chip with a main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. The safety area is internally powered by an internal regulated voltage generated by an internal voltage regulator that generates the internal regulated voltage from an external voltage while protecting against shorts of the external line delivering the external voltage. The safety area includes protection circuits that level shift external analog signals downward in voltage for monitoring within the safety area, the protection circuits serving to protect against shorts of the external line delivering the external analog signals.
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Patent Agency Ranking
公开(公告)号：US20240072670A1
公开(公告)日：2024-02-29
申请号：US18345525
申请日：2023-06-30
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano Castorina , Elena Brigo
IPC: H02M3/158 , G01R19/165 , H02M1/00
CPC classification number: H02M3/1582 , G01R19/16528 , H02M1/0009
Abstract: A controller for a buck-boost switching converter, which includes an inductor and a shunt resistor and is coupled to a load which draws a load current, includes a control circuit which performs charge and discharge cycles of the inductor. A first comparator stage generates a first signal which is indicative of a direction of the resistor current during the charge and discharge cycles. A low-pass filtering circuit generates a filtered electrical quantity based on a voltage on the shunt resistor during the charge and discharge cycles. A second comparator stage generates a second signal indicative of a comparison between the filtered electrical quantity and a reference electrical quantity. A detection stage detects the occurrence of an overcurrent in the load based on the second signal.
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公开(公告)号：US11885845B2
公开(公告)日：2024-01-30
申请号：US17678772
申请日：2022-02-23
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Gaudenzia Bagnati , Stefano Castorina , Valerio Bendotti
IPC: G01R31/02 , H03K17/687 , H03K5/24 , G01R31/54 , G01R19/165 , G01R31/28
CPC classification number: G01R31/2851 , G01R19/16571 , G01R31/54 , H03K5/24 , H03K17/6874 , H03K2217/0063 , H03K2217/0072
Abstract: An integrated circuit includes a plurality of power transistor driver channels for driving external loads. The driver channels can be selectively configured as high-side (HS) or low-side (LS) driver channels. The integrated circuit includes, for each driver channel, a respective on-state test circuit and a respective controller. The on-state test circuits can be selectively configured to test for HS overcurrent conditions, LS overcurrent conditions, HS open load conditions, and LS open load conditions.
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8.发明公开公开(公告)号：US20240088790A1
公开(公告)日：2024-03-14
申请号：US18451256
申请日：2023-08-17
Applicant: STMicroelectronics S.r.l.
Inventor： Ivan Floriani , Stefano Castorina , Giulia Altamura , Emanuele Moretti
CPC classification number: H02M3/1582 , H02M1/0035
Abstract: A control device for a switching voltage regulator having a switching circuit receives a set of measurement signals including a first measurement signal indicative of an output voltage of the switching voltage regulator. A burst-mode controller is configured to monitor the output voltage with respect to a first threshold and a second threshold higher than the first threshold, and to provide, in response, a burst signal. A driving-signal generation stage is configured to provide at least one switching control signal for the switching circuit based on the burst signal and the set of measurement signals. The driving-signal generation stage has a feedback module configured to provide a control signal based on the burst signal and an error signal indicative of a difference between the first measurement signal and a reference signal.
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公开(公告)号：US11719761B2
公开(公告)日：2023-08-08
申请号：US17407747
申请日：2021-08-20
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
CPC classification number: G01R31/64 , G01R27/2605 , G01R31/006
Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.
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公开(公告)号：US20230054951A1
公开(公告)日：2023-02-23
申请号：US17407725
申请日：2021-08-20
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
IPC: G01R19/10 , H03M1/12 , H03M3/00 , B60R21/017
Abstract: A system and method is provided for measuring a voltage drop at a node. In embodiments, a circuit includes an analog-to-digital converter, a current sink, and a controller. The input of the analog-to-digital converter and the input of the current sink is coupled to the node to be measured. A set point for the current sink is determined. The output of the analog-to-digital converter during the voltage drop is sampled. And a relative voltage drop value is computed by subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition. The current sink operating at the set point during the steady-state condition and during the voltage drop.
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