公开(公告)号：US20220293498A1

公开(公告)日：2022-09-15

申请号：US17688013

申请日：2022-03-07

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Fulvio Vittorio FONTANA ,  Davide Maria BENELLI ,  Jefferson Sismundo TALLEDO

IPC: H01L23/495 ,  H01L23/16 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor device, such as a Quad-Flat No-lead (QFN) package, includes a semiconductor chip arranged on a die pad of a leadframe. The leadframe has an array of electrically-conductive leads around the die pad. The leads in the array have distal ends facing away from the die pad as well as recessed portions at an upper surface of the leads. Resilient material, such as low elasticity modulus material, is present at the upper surface of the leads and filling the recessed portions. An insulating encapsulation is molded onto the semiconductor chip. The resilient material is sandwiched between the insulating encapsulation and the distal ends of the leads. This resilient material facilitates flexibility of the leads, making them suited for reliable soldering to an insulated metal substrate.

公开(公告)号：US20230068273A1

公开(公告)日：2023-03-02

申请号：US17889251

申请日：2022-08-16

Applicant: STMICROELECTRONICS, INC.

Inventor： Jefferson Sismundo TALLEDO

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: The present disclosure is directed to semiconductor packages manufactured utilizing a leadframe with varying thicknesses. The leadframe with varying thicknesses has a reduced likelihood of deformation while being handled during the manufacturing of the semiconductor packages as well as when being handled during a shipping process. The method of manufacturing is not required to utilize a leadframe tape based on the leadframe with varying thicknesses. This reduces the overall manufacturing costs of the semiconductor packages due to the reduced materials and steps in manufacturing the semiconductor packages as compared to a method that utilizes a leadframe tape to support a leadframe. The semiconductor packages may include leads of varying thicknesses formed by utilizing the leadframe of varying thicknesses to manufacture the semiconductor packages.

公开(公告)号：US20230253213A1

公开(公告)日：2023-08-10

申请号：US18303471

申请日：2023-04-19

Applicant: STMicroelectronics, Inc.

Inventor： Rennier RODRIGUEZ ,  Maiden Grace MAMING ,  Jefferson Sismundo TALLEDO

IPC: H01L21/48 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L21/4825 ,  H01L23/49513 ,  H01L23/562 ,  H01L23/49548 ,  H01L24/29 ,  H01L23/49503 ,  H01L23/49541

Abstract: The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

公开(公告)号：US20230411251A1

公开(公告)日：2023-12-21

申请号：US18330284

申请日：2023-06-06

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Sismundo TALLEDO

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49541 ,  H01L23/49534 ,  H01L23/3107 ,  H01L23/4952 ,  H01L21/565 ,  H01L24/48 ,  H01L2224/48247 ,  H01L2924/15321

Abstract: The present disclosure is directed to a thin substrate package and a lead frame method of fabricating the semiconductor package. The semiconductor package includes a first lead frame portion and a second lead frame portion. A substrate is positioned in a center opening between the first lead frame portion and the second lead frame portion, the substrate having a thickness less than or equal to 0.10-millimeters (mm). A first die having a plurality of wires is positioned on the substrate by an adhesive. A molding compound covers the first and second lead frame portions, the substrate, and the first die.

公开(公告)号：US20210179423A1

公开(公告)日：2021-06-17

申请号：US17103796

申请日：2020-11-24

Applicant: STMICROELECTRONICS, INC.

Inventor： Jefferson Sismundo TALLEDO

IPC: B81C1/00 ,  B81B7/00

Abstract: A semiconductor package that contains an application-specific integrated circuit (ASIC) die and a micro-electromechanical system (MEMS) die. The MEMS die and the ASIC die are coupled to a substrate that includes an opening that extends through the substrate and is in fluid communication with an air cavity positioned between and separating the MEMS die from the substrate. The opening exposes the air cavity to an external environment and, following this, the air cavity exposes a MEMS element of the MEMS die to the external environment. The air cavity separating the MEMS die from the substrate is formed with a method of manufacturing that utilizes a thermally decomposable die attach material.

公开(公告)号：US20240124300A1

公开(公告)日：2024-04-18

申请号：US18397930

申请日：2023-12-27

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Sismundo TALLEDO

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00309 ,  B81B7/0061 ,  B81B2201/0264 ,  B81B2201/0278 ,  B81B2207/012 ,  B81B2207/07 ,  B81C2201/0108 ,  B81C2201/0143 ,  B81C2201/0146

Abstract: A semiconductor package that contains an application-specific integrated circuit (ASIC) die and a micro-electromechanical system (MEMS) die. The MEMS die and the ASIC die are coupled to a substrate that includes an opening that extends through the substrate and is in fluid communication with an air cavity positioned between and separating the MEMS die from the substrate. The opening exposes the air cavity to an external environment and, following this, the air cavity exposes a MEMS element of the MEMS die to the external environment. The air cavity separating the MEMS die from the substrate is formed with a method of manufacturing that utilizes a thermally decomposable die attach material.

公开(公告)号：US20240113064A1

公开(公告)日：2024-04-04

申请号：US18233092

申请日：2023-08-11

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Sismundo TALLEDO

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/495

CPC classification number: H01L24/40 ,  H01L23/3675 ,  H01L23/49513 ,  H01L23/49575 ,  H01L24/32 ,  H01L2224/32238 ,  H01L2224/3224 ,  H01L2224/40091 ,  H01L2224/40155 ,  H01L2924/351

Abstract: An electronic device includes an integrated circuit (IC) with its second face bonded to a first surface of a first support. A conductive clip has a first portion that is elongate and extends across the IC, having its second surface bonded to a first face of the IC by a solder layer. A second portion of the clip extends from the first portion away from the IC toward a second support with the second surface bonded to a first surface of the second support. A first surface of the clip has a pattern formed therein including a depressed floor with fins extending upwardly therefrom. Through-holes extend through the depressed floor to the second surface of the clip. An encapsulating layer covers portions of the first and second supports, IC, and clip while leaving the first surface of the first portion exposed to permit heat to radiate away therefrom.

公开(公告)号：US20230420390A1

公开(公告)日：2023-12-28

申请号：US18339615

申请日：2023-06-22

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Sismundo TALLEDO

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L21/565 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4842 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49503

Abstract: A leadframe having extensions around an outer edge of a die pad are disclosed. More specifically, leadframes are created with a flange formed at the outer edge of the die pad and extending away from the die pad. The flange is bent, such that it is positioned at an angle with respect to the die pad. Leadframes are also created with anchoring posts formed adjacent the outer edge of the die pad and extending away from the die pad. The anchoring posts have a central thickness that is less than a thickness of first and second portions opposite the central portion. When the leadframe is incorporated into a package, molding compound completely surrounds each flange or anchoring post, which increases the bond strength between the leadframe and the molding compound due to increased contact area. The net result is a reduced possibility of delamination at edges of the die pad.

公开(公告)号：US20230187384A1

公开(公告)日：2023-06-15

申请号：US18168319

申请日：2023-02-13

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Sismundo TALLEDO

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/683

CPC classification number: H01L23/562 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/20 ,  H01L21/4857 ,  H01L24/19 ,  H01L21/6835 ,  H01L21/4853 ,  H01L2221/68372 ,  H01L2924/351 ,  H01L2224/214

Abstract: The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP) or a package containing a semiconductor die, with a die embedded within a substrate that is surrounded by an elastomer. The package includes nonconductive layers on surfaces of the substrate and the elastomer as well as conductive layers and conductive vias that extend through these layers to form electrical connections in the package. The package includes surfaces of the conductive material, which may be referred to as contacts. These surfaces of the conductive material are exposed on both sides of the package and allow the package to be mounted within an electronic device and have other electronic components coupled to the package, or allow the package to be included in a stacked configuration of semiconductor dice or packages.

公开(公告)号：US20210343658A1

公开(公告)日：2021-11-04

申请号：US17221374

申请日：2021-04-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Jefferson Sismundo TALLEDO

IPC: H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L21/48

Abstract: The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP) or a package containing a semiconductor die, with a die embedded within a substrate that is surrounded by an elastomer. The package includes nonconductive layers on surfaces of the substrate and the elastomer as well as conductive layers and conductive vias that extend through these layers to form electrical connections in the package. The package includes surfaces of the conductive material, which may be referred to as contacts. These surfaces of the conductive material are exposed on both sides of the package and allow the package to be mounted within an electronic device and have other electronic components coupled to the package, or allow the package to be included in a stacked configuration of semiconductor dice or packages.