公开(公告)号：US10983937B2

公开(公告)日：2021-04-20

申请号：US16802116

申请日：2020-02-26

Applicant: STMicroelectronics SA ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Olivier Ferrand ,  Daniel Olson ,  Anis Ben Said ,  Emmanuel Ardichvili

IPC: G06F13/364 ,  G06F13/362 ,  G06F13/42

Abstract: In accordance with an embodiment, a method for managing access to a bus shared by interfaces includes: when to the bus is granted to one of the interfaces, triggering a counting having a minimum counting period; and when at least one access request to the bus emanating from at least one other of the interfaces is received during the minimum counting period, releasing the access granted to the one of the interfaces, and creating an arbitration point at an end of the minimum counting period.

公开(公告)号：US20200293474A1

公开(公告)日：2020-09-17

申请号：US16802116

申请日：2020-02-26

Applicant: STMicroelectronics SA ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Olivier Ferrand ,  Daniel Olson ,  Anis Ben Said ,  Emmanuel Ardichvili

IPC: G06F13/364 ,  G06F13/362 ,  G06F13/42

Abstract: In accordance with an embodiment, a method for managing access to a bus shared by interfaces includes: when to the bus is granted to one of the interfaces, triggering a counting having a minimum counting period; and when at least one access request to the bus emanating from at least one other of the interfaces is received during the minimum counting period, releasing the access granted to the one of the interfaces, and creating an arbitration point at an end of the minimum counting period.

公开(公告)号：US20200026679A1

公开(公告)日：2020-01-23

申请号：US16504794

申请日：2019-07-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yassine El Khourassani ,  Patrick Valdenaire ,  Emmanuel Ardichvili

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/18

Abstract: A system on chip includes an interconnect circuit including at least p input interfaces and at least k output interfaces, p source devices respectively coupled to the p input interfaces and k access ports respectively coupled to the k output interfaces and belonging to a target that includes one or more target devices. Each source device is configured to deliver transactions to the target via one of the access ports. An associated memory of each access port is configured to temporarily store the transactions received by the access port. The target is configured to deliver, for each access port, a fill signal representative of a current fill level of its associated memory. A control circuit is configured to receive the fill signals from the access ports and select the access ports eligible to receive a transaction depending on the current fill levels.

公开(公告)号：US10740141B2

公开(公告)日：2020-08-11

申请号：US16362207

申请日：2019-03-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yassine El Khourassani ,  Patrick Valdenaire ,  Emmanuel Ardichvili

IPC: G06F12/0853 ,  G06F9/46 ,  G06F16/901 ,  G06F12/0886

Abstract: A system on chip includes an interconnect circuit having an input interface and a number of output interfaces. A source device is coupled to the input interface. A target device includes a sectorized addressable memory space and a number of access ports respectively coupled to the output interfaces. The source device is configured to deliver a transaction containing an address word to the target device.

公开(公告)号：US10698843B2

公开(公告)日：2020-06-30

申请号：US16274871

申请日：2019-02-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yassine El Khourassani ,  Patrick Valdenaire ,  Emmanuel Ardichvili

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/10

Abstract: An interconnect circuit includes a plurality of input interfaces and a plurality of output interfaces. A plurality of source devices are respectively coupled to the input interfaces. A target device has a plurality of access ports respectively coupled to the output interfaces. Each source device is configured to deliver transactions to the target device. Programmable control circuit is configured to deliver, to the interconnect circuit, a control word designating an access port assigned to this source device. The interconnect circuit is configured to route the transaction from the corresponding input interface to the output interface that is coupled to this access port and to deliver the transaction to the access port, the content of each transaction delivered to an access port being identical to the content of the corresponding transaction delivered by the source equipment whatever the selected access port.

公开(公告)号：US10997107B2

公开(公告)日：2021-05-04

申请号：US16504794

申请日：2019-07-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yassine El Khourassani ,  Patrick Valdenaire ,  Emmanuel Ardichvili

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/18

Abstract: A system on chip includes an interconnect circuit including at least p input interfaces and at least k output interfaces, p source devices respectively coupled to the p input interfaces and k access ports respectively coupled to the k output interfaces and belonging to a target that includes one or more target devices. Each source device is configured to deliver transactions to the target via one of the access ports. An associated memory of each access port is configured to temporarily store the transactions received by the access port. The target is configured to deliver, for each access port, a fill signal representative of a current fill level of its associated memory. A control circuit is configured to receive the fill signals from the access ports and select the access ports eligible to receive a transaction depending on the current fill levels.

公开(公告)号：US20200174964A1

公开(公告)日：2020-06-04

申请号：US16684296

申请日：2019-11-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Emmanuel Ardichvili ,  Laurent Lestringand ,  Patrick Valdenaire

IPC: G06F15/78 ,  G06F21/62 ,  G06F15/173

Abstract: A system includes a plurality of items of master equipment, each having a programing interface, and a plurality of slave equipment. An interconnect circuit is coupled between the items of master equipment and the items of slave equipment. Each transaction is assigned an attribute capable of taking on at least two attribute values corresponding to at least two states for the master equipment. Each item of slave equipment is associated with an identifier capable of taking on at least two values corresponding respectively to at least two properties for the slave equipment. Each item of master equipment automatically inherits the property of its programing interface. A filtering circuit is configured to, in the presence of a transaction intended for an item of slave equipment, compare the corresponding attribute value with an identifier value of the intended slave equipment and reject or not reject the transaction based on the comparison.

公开(公告)号：US11386037B2

公开(公告)日：2022-07-12

申请号：US16684296

申请日：2019-11-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Emmanuel Ardichvili ,  Laurent Lestringand ,  Patrick Valdenaire

IPC: G06F15/78 ,  G06F15/173 ,  G06F21/62 ,  G06F13/14

Abstract: A system includes a plurality of items of master equipment, each having a programing interface, and a plurality of slave equipment. An interconnect circuit is coupled between the items of master equipment and the items of slave equipment. Each transaction is assigned an attribute capable of taking on at least two attribute values corresponding to at least two states for the master equipment. Each item of slave equipment is associated with an identifier capable of taking on at least two values corresponding respectively to at least two properties for the slave equipment. Each item of master equipment automatically inherits the property of its programing interface. A filtering circuit is configured to, in the presence of a transaction intended for an item of slave equipment, compare the corresponding attribute value with an identifier value of the intended slave equipment and reject or not reject the transaction based on the comparison.

公开(公告)号：US20190317799A1

公开(公告)日：2019-10-17

申请号：US16362207

申请日：2019-03-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yassine El Khourassani ,  Patrick Valdenaire ,  Emmanuel Ardichvili

IPC: G06F9/46 ,  G06F12/0853 ,  G06F12/0886 ,  G06F16/901

Abstract: A system on chip includes an interconnect circuit having an input interface and a number of output interfaces. A source device is coupled to the input interface. A target device includes a sectorized addressable memory space and a number of access ports respectively coupled to the output interfaces. The source device is configured to deliver a transaction containing an address word to the target device.

公开(公告)号：US20190266108A1

公开(公告)日：2019-08-29

申请号：US16274871

申请日：2019-02-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yassine El Khourassani ,  Patrick Valdenaire ,  Emmanuel Ardichvili

IPC: G06F13/16 ,  G06F13/40

Abstract: An interconnect circuit includes a plurality of input interfaces and a plurality of output interfaces. A plurality of source devices are respectively coupled to the input interfaces. A target device has a plurality of access ports respectively coupled to the output interfaces. Each source device is configured to deliver transactions to the target device. Programmable control circuit is configured to deliver, to the interconnect circuit, a control word designating an access port assigned to this source device. The interconnect circuit is configured to route the transaction from the corresponding input interface to the output interface that is coupled to this access port and to deliver the transaction to the access port, the content of each transaction delivered to an access port being identical to the content of the corresponding transaction delivered by the source equipment whatever the selected access port.