公开(公告)号：US10983937B2

公开(公告)日：2021-04-20

申请号：US16802116

申请日：2020-02-26

Applicant: STMicroelectronics SA ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Olivier Ferrand ,  Daniel Olson ,  Anis Ben Said ,  Emmanuel Ardichvili

IPC: G06F13/364 ,  G06F13/362 ,  G06F13/42

Abstract: In accordance with an embodiment, a method for managing access to a bus shared by interfaces includes: when to the bus is granted to one of the interfaces, triggering a counting having a minimum counting period; and when at least one access request to the bus emanating from at least one other of the interfaces is received during the minimum counting period, releasing the access granted to the one of the interfaces, and creating an arbitration point at an end of the minimum counting period.

公开(公告)号：US20200293474A1

公开(公告)日：2020-09-17

申请号：US16802116

申请日：2020-02-26

Applicant: STMicroelectronics SA ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Olivier Ferrand ,  Daniel Olson ,  Anis Ben Said ,  Emmanuel Ardichvili

IPC: G06F13/364 ,  G06F13/362 ,  G06F13/42

Abstract: In accordance with an embodiment, a method for managing access to a bus shared by interfaces includes: when to the bus is granted to one of the interfaces, triggering a counting having a minimum counting period; and when at least one access request to the bus emanating from at least one other of the interfaces is received during the minimum counting period, releasing the access granted to the one of the interfaces, and creating an arbitration point at an end of the minimum counting period.

公开(公告)号：US11876732B2

公开(公告)日：2024-01-16

申请号：US17100505

申请日：2020-11-20

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Daniel Olson ,  Loic Pallardy ,  Nicolas Anquet

IPC: H04L41/0803 ,  H04L49/109 ,  G06F21/85

CPC classification number: H04L49/109 ,  G06F21/85 ,  H04L41/0803

Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.

公开(公告)号：US20210160193A1

公开(公告)日：2021-05-27

申请号：US17100505

申请日：2020-11-20

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Daniel Olson ,  Loic Pallardy ,  Nicolas Anquet

IPC: H04L12/933 ,  H04L12/24

Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.