公开(公告)号：US20200293474A1

公开(公告)日：2020-09-17

申请号：US16802116

申请日：2020-02-26

Applicant: STMicroelectronics SA ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Olivier Ferrand ,  Daniel Olson ,  Anis Ben Said ,  Emmanuel Ardichvili

IPC: G06F13/364 ,  G06F13/362 ,  G06F13/42

Abstract: In accordance with an embodiment, a method for managing access to a bus shared by interfaces includes: when to the bus is granted to one of the interfaces, triggering a counting having a minimum counting period; and when at least one access request to the bus emanating from at least one other of the interfaces is received during the minimum counting period, releasing the access granted to the one of the interfaces, and creating an arbitration point at an end of the minimum counting period.

公开(公告)号：US10983937B2

公开(公告)日：2021-04-20

申请号：US16802116

申请日：2020-02-26

Applicant: STMicroelectronics SA ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Olivier Ferrand ,  Daniel Olson ,  Anis Ben Said ,  Emmanuel Ardichvili

IPC: G06F13/364 ,  G06F13/362 ,  G06F13/42

Abstract: In accordance with an embodiment, a method for managing access to a bus shared by interfaces includes: when to the bus is granted to one of the interfaces, triggering a counting having a minimum counting period; and when at least one access request to the bus emanating from at least one other of the interfaces is received during the minimum counting period, releasing the access granted to the one of the interfaces, and creating an arbitration point at an end of the minimum counting period.

公开(公告)号：US11341603B2

公开(公告)日：2022-05-24

申请号：US16810486

申请日：2020-03-05

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Christophe Pinatel ,  Serge Mazer ,  Olivier Ferrand

IPC: G06T1/60 ,  G06N20/00 ,  G06K9/62 ,  G06T1/20 ,  G06V10/25

Abstract: An image processing electronic device includes a pipeline configured to process frames of image data; an internal memory coupled to the pipeline, wherein a set of descriptors arranged according to an order is stored in the internal memory, each descriptor of the set of descriptors is associated with a corresponding function to be activated by the pipeline on at least one frame of image data; a controller configured to read each descriptor of the set of descriptors sequentially and cyclically according to the order at a rate of at least one descriptor per one frame of image data and store information corresponding to each read descriptor, wherein the pipeline is configured to activate on each frame of image data, the function associated with each read descriptor based on the stored information.

公开(公告)号：US10402353B2

公开(公告)日：2019-09-03

申请号：US15701003

申请日：2017-09-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Dragos Davidescu ,  Sandrine Lendre ,  Olivier Ferrand

IPC: G06F13/16 ,  G06F1/3234 ,  G06F1/3293 ,  G06F13/24

Abstract: An embodiment system includes a first processor configured to process a suite of instructions and a second processor configured to process a subset of the suite of instructions. The system further includes a power management circuit configured to select the first processor or the second processor as a selected processor, the power management circuit being further configured to activate the selected processor or place the selected processor on standby. The system also includes a first peripheral device configured to generate a first interrupt signal, a switch configured to direct the first interrupt signal to the selected processor, and a first memory configured to store a first interrupt routine associated with the first interrupt signal, the selected processor being configured to execute the first interrupt routine in response to the first interrupt signal.

公开(公告)号：US20230126011A1

公开(公告)日：2023-04-27

申请号：US18045097

申请日：2022-10-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Olivier Ferrand ,  Jean-Francois Link

IPC: G06T1/60 ,  G06F12/10 ,  G06F12/0802

Abstract: In an embodiment a computer system includes at least one master module configured to process data having a format of N bits, a framebuffer configured to store pixel color component values of an image, the framebuffer having a resolution of N bits, each pixel being coded on P bits in the framebuffer and the pixels being stored one after another in the framebuffer and a memory management unit configured to control memory accesses of the at least one master module to the framebuffer, wherein the memory management unit is further configured to receive read memory access requests from the at least one master module, read at least one pixel in the framebuffer saved on P bits, and modify the format of the at least one read pixel by adding Q additional bits equal to a difference between N and P so as to format the at least one pixel on N bits before transmitting the at least one pixel to the at least one master module.

公开(公告)号：US11637947B2

公开(公告)日：2023-04-25

申请号：US16669951

申请日：2019-10-31

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Olivier Ferrand

IPC: H04N5/06 ,  G09G5/00 ,  H04N5/232 ,  G06F1/04 ,  G06F3/041 ,  H04N5/04

Abstract: A system includes an electronic module and an integrated circuit outside the electronic module. The integrated circuit is configured to generate a digital timing signal that emulates a first synchronization signal internal to the module and not available outside the module and to generate trigger signals based on the digital timing signal. A controller is configured to independently and autonomously perform control operations of the electronic module at times triggered by the trigger signals.

公开(公告)号：US20200302570A1

公开(公告)日：2020-09-24

申请号：US16810486

申请日：2020-03-05

Applicant: STMicroelectronics (Grenoble 20) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Christophe Pinatel ,  Serge Mazer ,  Olivier Ferrand

IPC: G06T1/60 ,  G06T1/20 ,  G06K9/32 ,  G06K9/62 ,  G06N20/00

Abstract: An image processing electronic device includes a pipeline configured to process frames of image data; an internal memory coupled to the pipeline, wherein a set of descriptors arranged according to an order is stored in the internal memory, each descriptor of the set of descriptors is associated with a corresponding function to be activated by the pipeline on at least one frame of image data; a controller configured to read each descriptor of the set of descriptors sequentially and cyclically according to the order at a rate of at least one descriptor per one frame of image data and store information corresponding to each read descriptor, wherein the pipeline is configured to activate on each frame of image data, the function associated with each read descriptor based on the stored information.

公开(公告)号：US20180189205A1

公开(公告)日：2018-07-05

申请号：US15701003

申请日：2017-09-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Dragos Davidescu ,  Sandrine Lendre ,  Olivier Ferrand

IPC: G06F13/16 ,  G06F1/32 ,  G06F13/24

CPC classification number: G06F13/1673 ,  G06F1/3243 ,  G06F1/3293 ,  G06F13/24 ,  Y02D10/122 ,  Y02D10/152

Abstract: An embodiment system includes a first processor configured to process a suite of instructions and a second processor configured to process a subset of the suite of instructions. The system further includes a power management circuit configured to select the first processor or the second processor as a selected processor, the power management circuit being further configured to activate the selected processor or place the selected processor on standby. The system also includes a first peripheral device configured to generate a first interrupt signal, a switch configured to direct the first interrupt signal to the selected processor, and a first memory configured to store a first interrupt routine associated with the first interrupt signal, the selected processor being configured to execute the first interrupt routine in response to the first interrupt signal.

公开(公告)号：US11895423B2

公开(公告)日：2024-02-06

申请号：US18187335

申请日：2023-03-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Olivier Ferrand

IPC: H04N5/06 ,  G09G5/00 ,  G06F1/04 ,  H04N23/80 ,  G06F3/041 ,  H04N5/04

CPC classification number: H04N5/06 ,  G06F1/04 ,  G09G5/006 ,  H04N23/80 ,  G06F3/0416 ,  G09G2310/08 ,  H04N5/04

Abstract: A system includes an electronic module and an integrated circuit outside the electronic module. The integrated circuit is configured to generate a digital timing signal that emulates a first synchronization signal internal to the module and not available outside the module and to generate trigger signals based on the digital timing signal. A controller is configured to independently and autonomously perform control operations of the electronic module at times triggered by the trigger signals.

公开(公告)号：US20230224426A1

公开(公告)日：2023-07-13

申请号：US18187335

申请日：2023-03-21

Applicant: STMicroelectronics(Rousset) SAS

Inventor： Olivier Ferrand

IPC: G09G5/00

CPC classification number: G09G5/006

Abstract: A system includes an electronic module and an integrated circuit outside the electronic module. The integrated circuit is configured to generate a digital timing signal that emulates a first synchronization signal internal to the module and not available outside the module and to generate trigger signals based on the digital timing signal. A controller is configured to independently and autonomously perform control operations of the electronic module at times triggered by the trigger signals.