公开(公告)号：US08002896B2

公开(公告)日：2011-08-23

申请号：US11248385

申请日：2005-10-11

申请人： Sakae Tanaka ,  Qunhua Wang ,  Sanjay Yadav ,  Quanyuan Shang ,  William R. Harshbarger

发明人： Sakae Tanaka ,  Qunhua Wang ,  Sanjay Yadav ,  Quanyuan Shang ,  William R. Harshbarger

IPC分类号： C23C16/04 ,  C23F1/00 ,  H01L21/306 ,  C23C16/06 ,  C23C16/22

CPC分类号： C23C16/042 ,  C23C16/4585 ,  C23C16/4586

摘要： A shadow frame and framing system for semiconductor fabrication equipment comprising a rectangular frame having four edges, the edges forming an interior lip with a top surface and an bottom engagement surface; and a cross beam disposed between at least two edges of the frame, the cross beam having a top surface and a bottom engagement surface, the engagement surface of the cross beam configured to be flush with the engagement surface of the lip; wherein one or more of the engagement surfaces are configured to cover metal interconnect bonding areas on a carrier disposed below the frame. The shadow frame is particularly useful in plasma enhanced chemical vapor deposition (PECVD) applications used to make active matrix liquid crystal displays (AMLCDs) and solar cells.

摘要翻译： 一种用于半导体制造设备的阴影框架和框架系统，包括具有四个边缘的矩形框架，所述边缘形成具有顶部表面和底部接合表面的内部唇部; 以及设置在所述框架的至少两个边缘之间的横梁，所述横梁具有顶表面和底部接合表面，所述横梁的接合表面被配置为与所述唇缘的接合表面齐平; 其中所述接合表面中的一个或多个构造成覆盖设置在所述框架下方的载体上的金属互连结合区域。 阴影框架在用于制造有源矩阵液晶显示器（AMLCD）和太阳能电池的等离子体增强化学气相沉积（PECVD）应用中特别有用。

公开(公告)号：US06960263B2

公开(公告)日：2005-11-01

申请号：US10136249

申请日：2002-04-25

申请人： Sakae Tanaka ,  Qunhua Wang ,  Sanjay Yadav ,  Quanyuan Shang ,  William R. Harshbarger

发明人： Sakae Tanaka ,  Qunhua Wang ,  Sanjay Yadav ,  Quanyuan Shang ,  William R. Harshbarger

IPC分类号： C23C16/04 ,  C23C16/458 ,  H01L21/205 ,  C23C16/00 ,  C23F1/00 ,  H01L21/306

CPC分类号： C23C16/042 ,  C23C16/4585 ,  C23C16/4586

摘要： A shadow frame and framing system for semiconductor fabrication equipment comprising a rectangular frame having four edges, the edges forming an interior lip with a top surface and an bottom engagement surface; and a cross beam disposed between at least two edges of the frame, the cross beam having a top surface and a bottom engagement surface, the engagement surface of the cross beam configured to be flush with the engagement surface of the lip; wherein one or more of the engagement surfaces are configured to cover metal interconnect bonding areas on a carrier disposed below the frame. The shadow frame is particularly useful in plasma enhanced chemical vapor deposition (PECVD) applications used to make active matrix liquid crystal displays (AMLCDs) and solar cells.

摘要翻译： 一种用于半导体制造设备的阴影框架和框架系统，包括具有四个边缘的矩形框架，所述边缘形成具有顶部表面和底部接合表面的内部唇部; 以及设置在所述框架的至少两个边缘之间的横梁，所述横梁具有顶表面和底部接合表面，所述横梁的接合表面被配置为与所述唇缘的接合表面齐平; 其中所述接合表面中的一个或多个构造成覆盖设置在所述框架下方的载体上的金属互连结合区域。 阴影框架在用于制造有源矩阵液晶显示器（AMLCD）和太阳能电池的等离子体增强化学气相沉积（PECVD）应用中特别有用。

公开(公告)号：US20060030088A1

公开(公告)日：2006-02-09

申请号：US11248385

申请日：2005-10-11

申请人： Sakae Tanaka ,  Qunhua Wang ,  Sanjay Yadav ,  Quanyuan Shang ,  William Harshbarger

发明人： Sakae Tanaka ,  Qunhua Wang ,  Sanjay Yadav ,  Quanyuan Shang ,  William Harshbarger

IPC分类号： H01L21/00

CPC分类号： C23C16/042 ,  C23C16/4585 ,  C23C16/4586

摘要： A shadow frame and framing system for semiconductor fabrication equipment comprising a rectangular frame having four edges, the edges forming an interior lip with a top surface and an bottom engagement surface; and a cross beam disposed between at least two edges of the frame, the cross beam having a top surface and a bottom engagement surface, the engagement surface of the cross beam configured to be flush with the engagement surface of the lip; wherein one or more of the engagement surfaces are configured to cover metal interconnect bonding areas on a carrier disposed below the frame. The shadow frame is particularly useful in plasma enhanced chemical vapor deposition (PECVD) applications used to make active matrix liquid crystal displays (AMLCDs) and solar cells.

公开(公告)号：US08305538B2

公开(公告)日：2012-11-06

申请号：US13239500

申请日：2011-09-22

申请人： Sakae Tanaka ,  Toshiyuki Samejima

发明人： Sakae Tanaka ,  Toshiyuki Samejima

IPC分类号： G02F1/1343

CPC分类号： G02F1/134363 ,  G02F1/133707 ,  G02F2001/134372 ,  G02F2001/136231 ,  G02F2001/136236 ,  G02F2001/13712 ,  G09G3/3648 ,  G09G2310/0218 ,  G09G2310/0283

摘要： A super large wide-angle high-speed response liquid crystal display apparatus manufactured by using a photolithographic procedure for three times. The invention adopts a halftone exposure technology to form a gate electrode, a common electrode, a pixel electrode and a contact pad, and then uses the halftone exposure technology to form a silicon (Si) island and a contact hole, and a general exposure technology to form a source electrode, a drain electrode and an orientation control electrode. A passivation layer uses a masking deposition method. A film is formed by using a P-CVD method, or a protective area is formed at a local area by using an ink coating method or spray method, and a TFT array substrate used for the super large wide-angle high-speed response liquid crystal display apparatus manufactured by using a photolithographic procedure for three times can be produced.

公开(公告)号：US20120038875A1

公开(公告)日：2012-02-16

申请号：US13239500

申请日：2011-09-22

申请人： Sakae Tanaka ,  Toshiyuki Samejima

发明人： Sakae Tanaka ,  Toshiyuki Samejima

IPC分类号： G02F1/1333

CPC分类号： G02F1/134363 ,  G02F1/133707 ,  G02F2001/134372 ,  G02F2001/136231 ,  G02F2001/136236 ,  G02F2001/13712 ,  G09G3/3648 ,  G09G2310/0218 ,  G09G2310/0283

摘要： A super large wide-angle high-speed response liquid crystal display apparatus manufactured by using a photolithographic procedure for three times. The invention adopts a halftone exposure technology to form a gate electrode, a common electrode, a pixel electrode and a contact pad, and then uses the halftone exposure technology to form a silicon (Si) island and a contact hole, and a general exposure technology to form a source electrode, a drain electrode and an orientation control electrode. A passivation layer uses a masking deposition method. A film is formed by using a P-CVD method, or a protective area is formed at a local area by using an ink coating method or spray method, and a TFT array substrate used for the super large wide-angle high-speed response liquid crystal display apparatus manufactured by using a photolithographic procedure for three times can be produced.

摘要翻译： 一种超大型广角高速响应液晶显示装置，通过使用光刻步骤三次制造。 本发明采用半色调曝光技术形成栅电极，公共电极，像素电极和接触焊盘，然后使用半色调曝光技术形成硅（Si）岛和接触孔，以及一般曝光技术 以形成源电极，漏电极和取向控制电极。 钝化层使用掩模沉积方法。 通过使用P-CVD法形成膜，或者通过使用油墨涂布法或喷雾法在局部区域形成保护区域，以及用于超大型广角高速响应液体的TFT阵列基板 可以制造通过使用光刻工艺制造三次的晶体显示装置。

公开(公告)号：US07016001B2

公开(公告)日：2006-03-21

申请号：US10100372

申请日：2002-03-14

申请人： Sakae Tanaka ,  Seok Lyul Lee

发明人： Sakae Tanaka ,  Seok Lyul Lee

IPC分类号： G02F1/1333

CPC分类号： G02F1/1393 ,  G02F1/133512 ,  G02F1/133707 ,  G02F2001/136222

摘要： An MVA-LCD device has a first glass substrate and a second glass substrate disposed in parallel to each other. A plurality of transverse-extending scanning electrodes and lengthwise-extending signal electrodes are patterned on the first glass substrate to define a plurality of pixel areas. A color resin layer is formed on the signal electrodes, and an organic insulator is formed on the color resin layer. Also, at least a first protrusion is formed in the organic insulator within each pixel area. A plurality of pixel electrodes is formed on the organic insulator and the first protrusions to cover each pixel area of the first glass substrate.

公开(公告)号：US06833897B2

公开(公告)日：2004-12-21

申请号：US10127012

申请日：2002-04-19

申请人： Seok Lyul Lee ,  Sakae Tanaka

发明人： Seok Lyul Lee ,  Sakae Tanaka

IPC分类号： G02F11343

CPC分类号： G02F1/134363 ,  G02F2001/136222

摘要： An in-plane switching mode liquid crystal display (IPS-LCD) device. The device has a lower glass substrate and an upper glass substrate disposed parallel to each other. A plurality of transverse-extending scanning electrodes and a plurality of lengthwise-extending signal electrodes are patterned on the lower glass substrate to define a plurality of pixel areas. In each pixel area, at least one lengthwise-extending pixel electrode and at least two lengthwise-extending common electrodes are formed on the same level plane of the lower glass substrate, wherein the pixel electrode is disposed at the interval between the common electrodes. Also, a color resin layer is sandwiched between the signal electrodes and the common electrodes. Moreover, the common electrode is located over the signal electrode across two adjacent pixel areas.

摘要翻译： 平面开关模式液晶显示器（IPS-LCD）装置。 该装置具有彼此平行布置的下玻璃基板和上玻璃基板。 多个横向延伸的扫描电极和多个纵向延伸的信号电极在下部玻璃基板上图案化以限定多个像素区域。 在每个像素区域中，至少一个纵向延伸的像素电极和至少两个纵向延伸的公共电极形成在下部玻璃基板的同一水平面上，其中像素电极以公共电极之间的间隔设置。 此外，彩色树脂层夹在信号电极和公共电极之间。 此外，公共电极位于跨越两个相邻像素区域的信号电极上方。

公开(公告)号：US06661493B2

公开(公告)日：2003-12-09

申请号：US10121680

申请日：2002-04-15

申请人： Ching Chao Chang ,  Sakae Tanaka

发明人： Ching Chao Chang ,  Sakae Tanaka

IPC分类号： G02F11343

CPC分类号： G02F1/134363

摘要： A pixel area of an in-plane switching mode LCD (IPS-LCD) device has at least two common electrodes extending along Y-axis direction and at least a pixel electrode extending along Y-axis direction, in which the pixel electrode is disposed between the two adjacent common electrodes in parallel. The common electrode and the pixel electrode have the same profile that is connected by a first strip-shaped segment, a second strip-shaped segment, a third strip-shaped segment and a fourth strip-shaped segment in sequence. The first segment is not parallel to the second segment, the first segment is not parallel to the third segment, the second segment is not parallel to the fourth segment, and the third segment is not parallel to the fourth segment.

摘要翻译： 平面内切换模式LCD（IPS-LCD）装置的像素区域具有沿着Y轴方向延伸的至少两个公共电极和至少沿Y轴方向延伸的像素电极，其中像素电极位于 两个相邻的公共电极并联。 公共电极和像素电极具有相同的轮廓，其由第一条形段，第二条形段，第三条形段和第四条形段依次连接。 第一段不平行于第二段，第一段不平行于第三段，第二段不平行于第四段，第三段不平行于第四段。

公开(公告)号：US5109260A

公开(公告)日：1992-04-28

申请号：US564815

申请日：1990-08-08

申请人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

发明人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L29/41733 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78624

摘要： A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulation layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film transistors to each other; and source wiring for connecting the source electrodes of the silicon thin film transistors to each other.

摘要翻译： 硅薄膜晶体管阵列包括阵列状形式的多个硅薄膜晶体管，每个硅薄膜晶体管包括绝缘基板，形成在绝缘基板上的栅电极，形成在绝缘基板上的栅绝缘层， 栅电极，一对第一杂质含有在栅极绝缘层上形成的跨越栅电极的端部的硅层，形成在一对第一杂质上的本征硅层含有硅层和在 一对第一杂质之间的栅极绝缘层包含硅层，以便连接一对第一杂质含硅层，形成在本征硅层上的保护绝缘层，以及形成在源极电极和漏电极 该对第一杂质的接触部分含有硅层; 用于将硅薄膜晶体管的栅电极彼此连接的栅极布线; 以及用于将硅薄膜晶体管的源电极彼此连接的源极布线。

公开(公告)号：US5065202A

公开(公告)日：1991-11-12

申请号：US534003

申请日：1990-06-04

申请人： Sakae Tanaka ,  Yoshiaki Watanabe

发明人： Sakae Tanaka ,  Yoshiaki Watanabe

IPC分类号： H01L23/52 ,  G02F1/136 ,  G02F1/1368 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/78669 ,  H01L27/1214

摘要： An amorphous silicon thin film transistor array substrate is formed on an insulating substrate with a gate insulating layer, as gate wiring itnerconnecting gate electrodes and source wiring interconnecting source electrodes. The gate insulating layer is provided in a lower layer of a terminal part of the source wiring. In the process for forming the array, the gate insulating layer is formed in a portion of the structure other than the terminal part of the gate, and the terminal part of the source wiring is formed on the gate insulating layer.

摘要翻译： 在具有栅极绝缘层的绝缘基板上形成非晶硅薄膜晶体管阵列基板，作为栅极布线与栅极电极和源极布线互连源极电极连接。 栅极绝缘层设置在源极配线的端子部的下层。 在形成阵列的工艺中，栅极绝缘层形成在除了栅极的端子部分之外的结构的一部分中，源极配线的端子部分形成在栅极绝缘层上。