公开(公告)号：US12123087B2

公开(公告)日：2024-10-22

申请号：US17573647

申请日：2022-01-12

Applicant: United Semiconductor Japan Co., Ltd.

Inventor： Satoshi Inagaki

IPC: C23C14/04 ,  C23C16/04 ,  G03F7/00

CPC classification number: C23C14/044 ,  C23C16/042 ,  G03F7/70216

Abstract: A mask structure for a deposition device includes first segments and second segments. The first segments are arranged in a direction surrounding a central axis and separated from one another. The second segments are disposed above the first segments. Each of the second segments overlaps two of the first segments adjacent to each other in a vertical direction parallel to an extending direction of the central axis. A deposition device includes a process chamber, a stage, and the mask structure. The stage is at least partially disposed in the process chamber and includes a holding structure of a substrate. The mask structure is disposed in the process chamber, located over the stage, and covers a peripheral region of the substrate to be held on the stage. An operation method of the deposition device includes horizontally adjusting positions of the first segments and the second segments respectively between different deposition processes.

公开(公告)号：US12077852B2

公开(公告)日：2024-09-03

申请号：US17240395

申请日：2021-04-26

Applicant: Applied Materials, Inc.

Inventor： Aykut Aydin ,  Rui Cheng ,  Karthik Janakiraman

IPC: C23C16/04 ,  C23C16/18 ,  C23C16/40 ,  C23C22/77 ,  C23C22/82

CPC classification number: C23C16/042 ,  C23C16/18 ,  C23C16/402 ,  C23C22/77 ,  C23C22/82

Abstract: Exemplary deposition methods may include delivering a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include delivering a dopant-containing precursor with the boron-containing precursor. The dopant-containing precursor may include a metal. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a doped-boron material on a substrate disposed within the processing region of the semiconductor processing chamber. The doped-boron material may include greater than or about 80 at. % of boron in the doped-boron material.

公开(公告)号：US20240254618A1

公开(公告)日：2024-08-01

申请号：US18381191

申请日：2023-10-18

Applicant: Darwin Precisions Corporation

Inventor： HAN-FANG LI ,  CHIAO-LING HUANG

IPC: C23C16/04

CPC classification number: C23C16/042

Abstract: The present invention provides a metal mask structure, including: an outer frame, a protrusion region, and a first connection region. The outer frame surrounds and defines a central hollowed-out region and includes at least a first side frame. The protrusion region protrudes from the first side frame toward the central hollowed-out region, and is provided with at least one hole. The protrusion region is connected to the first side frame at a connection side edge. The first connection region connects the protrusion region to the first side frame at one end of the connection side edge, and includes a first side edge, a second side edge, and a third side edge. The first side edge continues from the connection side edge, the second side edge extends transversely from a junction of the first side edge and the connection side edge toward the central hollowed-out region, and two ends of the third side edge are respectively connected to endpoints of the first side edge and the second side edge away from the connection side edge.

公开(公告)号：US20240249951A1

公开(公告)日：2024-07-25

申请号：US18418757

申请日：2024-01-22

Applicant: Tokyo Electron Limited

Inventor： Kosuke YOSHIHARA ,  Yuichi TERASHITA ,  Yukinobu OTSUKA ,  Shinsuke TAKAKI ,  Hiroki TADATOMO ,  Naoki SHIBATA

IPC: H01L21/308 ,  C23C16/04 ,  C23C16/455 ,  C23C16/46 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/3081 ,  C23C16/042 ,  C23C16/45517 ,  C23C16/46 ,  H01L21/02491 ,  H01L21/3247

Abstract: A substrate treatment method includes: developing a substrate which has a coating film of a metal-containing resist formed thereon and has been subjected to an exposure treatment and a heat treatment after the exposure treatment, the developing including: exposing the substrate to an acid atmosphere being an atmosphere containing gas of a weak acid under a pressure of an atmospheric pressure or higher; and removing a product produced by a reaction between the metal-containing resist and the gas of the weak acid, by heating the substrate.

公开(公告)号：US12037678B2

公开(公告)日：2024-07-16

申请号：US16978078

申请日：2019-11-12

Applicant: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiangnan Pan ,  Zhiliang Jiang

IPC: C23C16/04 ,  B05C21/00 ,  G03F7/00 ,  H10K50/84

CPC classification number: C23C16/042 ,  B05C21/005 ,  G03F7/0015 ,  H10K50/84

Abstract: A mask is provided. The mask includes at least one first mask strip. The first mask strip includes a main body and at least one reinforced rib; the main body includes a plate surface defined by a first direction and a second direction, the first direction intersects with the second direction, and the main body extends along the first direction; and the at least one reinforced rib is on the plate surface of the main body and extends along the first direction, and a width of the at least one reinforced rib in the second direction is smaller than a width of the main body in the second direction.

公开(公告)号：US12033850B2

公开(公告)日：2024-07-09

申请号：US17991380

申请日：2022-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY ,  NATIONAL TAIWAN NORMAL UNIVERSITY

Inventor： Chun-Yi Chou ,  Po-Hsien Cheng ,  Tse-An Chen ,  Miin-Jang Chen

IPC: H01L21/02 ,  C23C16/04 ,  H01L21/28 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/0228 ,  C23C16/042 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/76224 ,  H01L21/76829 ,  H01L21/76877 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A device includes a conductive feature, a first dielectric layer, a via, an etch stop layer, a second dielectric layer, and a conductive line. The first dielectric layer is above the conductive feature. The via is in the first dielectric layer and above the conductive feature. The etch stop layer is above the first dielectric layer. A side surface of the etch stop layer is coterminous with a sidewall of the via. The second dielectric layer is above the etch stop layer. The conductive line is in the second dielectric layer and over the via. The conductive line is in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.

公开(公告)号：US20240141491A1

公开(公告)日：2024-05-02

申请号：US18070834

申请日：2022-11-29

Applicant: General Electric Company

Inventor： Thomas John Kilyk ,  Thomas Edward Mantkowski ,  Micah Thomas Rainwater

IPC: C23C16/458 ,  C23C16/04

CPC classification number: C23C16/458 ,  C23C16/042

Abstract: A deposition support apparatus and method for coating a component, the deposition support apparatus including a mask container defining an interior and having an opening providing access to the interior. At least one barrier plate with a component aperture wherein the component extends through the component aperture with a first portion of the component located within the interior and a second portion of the component extending above the at least one barrier plate.

公开(公告)号：US11970765B2

公开(公告)日：2024-04-30

申请号：US17426714

申请日：2020-01-15

Applicant: Ionautics AB

Inventor： Henrik Pedersen ,  Hama Nadhom

IPC: C23C16/44 ,  C23C16/02 ,  C23C16/04 ,  C23C16/455 ,  C23C16/48 ,  C23C18/14 ,  H01J37/32 ,  H01L21/285

CPC classification number: C23C16/0272 ,  C23C16/0227 ,  C23C16/042 ,  C23C16/45523 ,  C23C16/487 ,  C23C18/145 ,  H01J37/32422 ,  H01L21/28506 ,  H01J2237/3321

Abstract: The present disclosure relates to a method for chemical vapour deposition on a substrate, the method comprising a precursor step and a reactant step, wherein the precursor step comprises chemisorbing a layer of precursor molecules on the substrate (170), and wherein the reactant step comprises adding to at least part of the substrate (170) surface species able to reduce the precursor molecule, whereby at least a part of the reduced precursor molecule is deposited on the substrate (170) surface, characterized by applying by means of a voltage source (130) a positive bias to at least part of the substrate (170) surface during at least part of the reactant step, wherein the step of adding the reducing species comprises providing by means of an electron source (150) electrons as free particles, whereby during the reactant step a closed electrical circuit is formed as the free electrons are transmitted to the substrate (170) surface.

公开(公告)号：US11955337B2

公开(公告)日：2024-04-09

申请号：US17298332

申请日：2019-07-12

Applicant: TOKYO ELECTRON LIMITED

Inventor： Toru Hisamatsu ,  Takayuki Katsunuma ,  Shinya Ishikawa ,  Yoshihide Kihara ,  Masanobu Honda

IPC: H01L21/033 ,  H01L21/311 ,  C23C16/04

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  C23C16/042

Abstract: A substrate processing method includes: providing a substrate including a mask; forming a film on the mask; forming a reaction layer on a surface layer of the film; and removing the reaction layer by applying energy to the reaction layer.

公开(公告)号：US11923251B2

公开(公告)日：2024-03-05

申请号：US17314804

申请日：2021-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hsiu Perng ,  Kai-Chieh Yang ,  Zhi-Chang Lin ,  Teng-Chun Tsai ,  Wei-Hao Wu

IPC: H01L21/8238 ,  C23C16/04 ,  H01L21/28 ,  H01L21/768 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823842 ,  C23C16/042 ,  H01L21/28079 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/76829 ,  H01L21/823821 ,  H01L29/4941 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.