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    GATE DRIVING CIRCUIT AND DISPLAY APPARATUS INCLUDING THE SAME
    1.
    发明申请
    GATE DRIVING CIRCUIT AND DISPLAY APPARATUS INCLUDING THE SAME 有权
    闸门驱动电路和显示装置，包括它们

    公开(公告)号：US20160210927A1

    公开(公告)日：2016-07-21

    申请号：US14936434

    申请日：2015-11-09

    Applicant: Samsung Display Co., Ltd.

    Inventor： Sehyoung CHO ,  Kyung-hoon KIM ,  Dongwoo KIM ,  Ilgon KIM ,  Kangmoon JO

    IPC: G09G3/36 ,  G06F1/04

    CPC classification number: G09G3/3677 ,  G09G3/3614 ,  G09G3/3696 ,  G09G2310/0251 ,  G09G2310/08

    Abstract: A gate driving circuit includes a plurality of stages for providing gate signals, wherein a k-th stage (k is a natural number greater than 3) includes a first output transistor including a control electrode connected to a first node, an input electrode for receiving a clock signal, and an output electrode for outputting a k-th gate signal, a second output transistor including a control electrode connected to the first node, an input electrode for receiving the clock signal, and an output electrode for outputting a k-th carry signal, a pull-down unit connected to a discharge node to pull down the output electrode of the first output transistor in response to a signal of the discharge node, and a discharge unit configured to output a (k−1)-th carry signal output from a (k−1)-th stage to the discharge node in response to a (k+1)-th carry signal output from a (k+1)-th stage.

    Abstract translation: 栅极驱动电路包括用于提供栅极信号的多个级，其中第k级（k是大于3的自然数）包括第一输出晶体管，其包括连接到第一节点的控制电极，用于接收的输入电极 时钟信号和用于输出第k个门信号的输出电极，包括连接到第一节点的控制电极的第二输出晶体管，用于接收时钟信号的输入电极和用于输出第k个门极信号的输出电极 连接到放电节点的下拉单元，以响应于放电节点的信号来拉低第一输出晶体管的输出电极;以及放电单元，被配置为输出第（k-1）个进位 响应从第（k + 1）级输出的第（k + 1）个进位信号从第（k-1）级到放电节点的信号输出。

    SCAN DRIVER
    2.
    发明申请
    SCAN DRIVER 有权
    扫描驱动器

    公开(公告)号：US20160247479A1

    公开(公告)日：2016-08-25

    申请号：US15019741

    申请日：2016-02-09

    Applicant: Samsung Display Co., Ltd.

    Inventor： Sehyoung CHO ,  Kyunghoon KIM ,  Dongwoo KIM ,  Ilgon KIM ,  Kangmoon JO ,  Hyunjoon KIM

    IPC: G09G3/36

    CPC classification number: G09G3/3677 ,  G09G2310/0286

    Abstract: There is provided a scan driver. The scan driver includes stages. An ith (i is a natural number) stage circuit includes an output unit, a controller configured to control the voltage of the second node in response to a kth (k is a natural number) clock signal supplied to a second input terminal, and an input unit configured to control the voltages of the first node and the second node in response to a carry signal of a previous stage that is supplied to a third input terminal and a carry signal of at least one next stage. The kth clock signal maintains a gate on voltage at a point of time at which a voltage of the jth clock signal is changed to a gate on voltage.

    Abstract translation: 提供了扫描驱动程序。 扫描驱动程序包括阶段。 第i（i是自然数）级电路包括输出单元，被配置为响应于提供给第二输入端的第k（k是自然数）时钟信号来控制第二节点的电压的控制器，以及 输入单元，被配置为响应于提供给第三输入端的先前级的进位信号和至少一个下一级的进位信号来控制第一节点和第二节点的电压。 第k个时钟信号在第j个时钟信号的电压变为栅极导通电压的时间点处保持栅极导通电压。

    DISPLAY DEVICE
    3.
    发明申请
    DISPLAY DEVICE 有权
    显示设备

    公开(公告)号：US20130307758A1

    公开(公告)日：2013-11-21

    申请号：US13721980

    申请日：2012-12-20

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： Ilgon KIM ,  Kyung-Hoon KIM ,  SEON YOUNG CHOI ,  Jangmi KANG

    IPC: G09G3/22

    CPC classification number: G09G3/22 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0281 ,  Y10T29/49002

    Abstract: A display device includes a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction, a plurality of sub-gate lines corresponding to the plurality of gate lines and extending in a first direction to be adjacent to a corresponding gate line of the plurality of gate lines, a gate driver configured to drive the plurality of gate lines, a data driver configured to drive the plurality of data lines, and a plurality of pixels arranged in a display area, where an end of each of the plurality of gate lines extends in the first direction from the gate driver is electrically connected to a center portion of a corresponding sub-gate line in the first direction.

    Abstract translation: 显示装置包括沿第一方向延伸的多条栅极线，沿第二方向延伸的多条数据线，与该多条栅极线对应的多条子栅极线，并沿与第一方向相邻的第一方向延伸 多个栅极线的对应的栅极线，被配置为驱动多个栅极线的栅极驱动器，被配置为驱动多个数据线的数据驱动器和布置在显示区域中的多个像素，其中， 从栅极驱动器沿第一方向延伸的多条栅极线中的每一条电路都沿第一方向电连接到对应的子栅极线的中心部分。

    GATE DRIVING UNIT
    5.
    发明申请
    GATE DRIVING UNIT 有权
    门驱动单元

    公开(公告)号：US20160232866A1

    公开(公告)日：2016-08-11

    申请号：US14821329

    申请日：2015-08-07

    Applicant: Samsung Display Co., LTD.

    Inventor： Sehyoung CHO ,  Kyung-hoon KIM ,  Dongwoo KIM ,  Ilgon KIM ,  Meehye JUNG ,  Kangmoon JO

    IPC: G09G3/36 ,  H03K17/56

    CPC classification number: G09G3/3677 ,  G09G3/3266 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2330/08 ,  H03K17/56

    Abstract: Provided is a gate driving unit including: a plurality of stages configured to be activated sequentially so as to generate gate signals; and a plurality of repair blocks having sizes smaller than the corresponding stages and configured to repair defects of the stages. Each of the repair blocks is disposed proximate to two or more stages so as to be configured to repair defects in the two or more stages.

    Abstract translation: 提供一种栅极驱动单元，包括：多个级，被配置为顺序地被激活以产生门信号; 以及具有小于相应级的尺寸的多个修复块，并被配置为修复所述级的缺陷。 每个修理块设置成接近两个或更多个阶段，以便构造成修复两个或更多个阶段中的缺陷。

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