公开(公告)号：US20160210927A1

公开(公告)日：2016-07-21

申请号：US14936434

申请日：2015-11-09

Applicant: Samsung Display Co., Ltd.

Inventor： Sehyoung CHO ,  Kyung-hoon KIM ,  Dongwoo KIM ,  Ilgon KIM ,  Kangmoon JO

IPC: G09G3/36 ,  G06F1/04

CPC classification number: G09G3/3677 ,  G09G3/3614 ,  G09G3/3696 ,  G09G2310/0251 ,  G09G2310/08

Abstract: A gate driving circuit includes a plurality of stages for providing gate signals, wherein a k-th stage (k is a natural number greater than 3) includes a first output transistor including a control electrode connected to a first node, an input electrode for receiving a clock signal, and an output electrode for outputting a k-th gate signal, a second output transistor including a control electrode connected to the first node, an input electrode for receiving the clock signal, and an output electrode for outputting a k-th carry signal, a pull-down unit connected to a discharge node to pull down the output electrode of the first output transistor in response to a signal of the discharge node, and a discharge unit configured to output a (k−1)-th carry signal output from a (k−1)-th stage to the discharge node in response to a (k+1)-th carry signal output from a (k+1)-th stage.

Abstract translation: 栅极驱动电路包括用于提供栅极信号的多个级，其中第k级（k是大于3的自然数）包括第一输出晶体管，其包括连接到第一节点的控制电极，用于接收的输入电极 时钟信号和用于输出第k个门信号的输出电极，包括连接到第一节点的控制电极的第二输出晶体管，用于接收时钟信号的输入电极和用于输出第k个门极信号的输出电极 连接到放电节点的下拉单元，以响应于放电节点的信号来拉低第一输出晶体管的输出电极;以及放电单元，被配置为输出第（k-1）个进位 响应从第（k + 1）级输出的第（k + 1）个进位信号从第（k-1）级到放电节点的信号输出。

公开(公告)号：US20160232866A1

公开(公告)日：2016-08-11

申请号：US14821329

申请日：2015-08-07

Applicant: Samsung Display Co., LTD.

Inventor： Sehyoung CHO ,  Kyung-hoon KIM ,  Dongwoo KIM ,  Ilgon KIM ,  Meehye JUNG ,  Kangmoon JO

IPC: G09G3/36 ,  H03K17/56

CPC classification number: G09G3/3677 ,  G09G3/3266 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2330/08 ,  H03K17/56

Abstract: Provided is a gate driving unit including: a plurality of stages configured to be activated sequentially so as to generate gate signals; and a plurality of repair blocks having sizes smaller than the corresponding stages and configured to repair defects of the stages. Each of the repair blocks is disposed proximate to two or more stages so as to be configured to repair defects in the two or more stages.

Abstract translation: 提供一种栅极驱动单元，包括：多个级，被配置为顺序地被激活以产生门信号; 以及具有小于相应级的尺寸的多个修复块，并被配置为修复所述级的缺陷。 每个修理块设置成接近两个或更多个阶段，以便构造成修复两个或更多个阶段中的缺陷。

公开(公告)号：US20160190223A1

公开(公告)日：2016-06-30

申请号：US14805765

申请日：2015-07-22

Applicant: Samsung Display Co., Ltd.

Inventor： Gyungsoon PARK ,  Minjae JEONG ,  Keumnam KIM ,  Sehyoung CHO ,  Jongho HONG

IPC: H01L27/32 ,  H01L51/00 ,  G09G3/32

CPC classification number: H01L27/3276 ,  G09G3/2003 ,  G09G2300/0426 ,  G09G2380/02 ,  H01L51/0097 ,  H01L2251/5338 ,  Y02E10/549

Abstract: A flexible display is disclosed. In one aspect, the display includes at least one first pattern including a plurality of display elements configured to display an image and extending in a first direction. The display device also includes at least one second pattern extending in a second direction and overlapping at least a portion of the first pattern. The second pattern has a curved shape in the first direction and the second direction crosses the first direction. The first and second patterns form at least one cavity region defining a space therebetween and the first and second patterns form a mesh structure.

Abstract translation: 公开了一种柔性显示器。 在一个方面，显示器包括至少一个第一图案，其包括被配置为显示图像并在第一方向上延伸的多个显示元件。 显示装置还包括沿第二方向延伸并与第一图案的至少一部分重叠的至少一个第二图案。 第二图案在第一方向上具有弯曲形状，而第二方向与第一方向交叉。 第一和第二图案形成至少一个在其间限定空间的空腔区域，并且第一和第二图案形成网格结构。

公开(公告)号：US20190340991A1

公开(公告)日：2019-11-07

申请号：US16518710

申请日：2019-07-22

Applicant: Samsung Display Co., Ltd.

Inventor： Junghwan HWANG ,  Sehyoung CHO

IPC: G09G3/36

Abstract: A gate driving circuit includes: a plurality of stages to provide gate signals to gate lines of a display panel, a k-th stage, where k is a natural number greater than or equal to 2, from among the plurality of stages being configured: to receive a clock signal, a (k−1)th carry signal from a (k−1)th stage, a (k+1)th carry signal from a (k+1)th stage, a (k+2)th carry signal from a (k+2)th stage, a first voltage, and a second voltage, the clock signal being a pulse signal in which a high voltage and a third voltage appear periodically, and the third voltage having a lower voltage level than those of the first voltage and the second voltage; and to output a k-th gate signal and a k-th carry signal.

公开(公告)号：US20160247479A1

公开(公告)日：2016-08-25

申请号：US15019741

申请日：2016-02-09

Applicant: Samsung Display Co., Ltd.

Inventor： Sehyoung CHO ,  Kyunghoon KIM ,  Dongwoo KIM ,  Ilgon KIM ,  Kangmoon JO ,  Hyunjoon KIM

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2310/0286

Abstract: There is provided a scan driver. The scan driver includes stages. An ith (i is a natural number) stage circuit includes an output unit, a controller configured to control the voltage of the second node in response to a kth (k is a natural number) clock signal supplied to a second input terminal, and an input unit configured to control the voltages of the first node and the second node in response to a carry signal of a previous stage that is supplied to a third input terminal and a carry signal of at least one next stage. The kth clock signal maintains a gate on voltage at a point of time at which a voltage of the jth clock signal is changed to a gate on voltage.

Abstract translation: 提供了扫描驱动程序。 扫描驱动程序包括阶段。 第i（i是自然数）级电路包括输出单元，被配置为响应于提供给第二输入端的第k（k是自然数）时钟信号来控制第二节点的电压的控制器，以及 输入单元，被配置为响应于提供给第三输入端的先前级的进位信号和至少一个下一级的进位信号来控制第一节点和第二节点的电压。 第k个时钟信号在第j个时钟信号的电压变为栅极导通电压的时间点处保持栅极导通电压。