Abstract:
A thermal treatment method for a display apparatus includes providing an acceptor substrate on a substrate stage, providing on the acceptor substrate a pattern mask including a transfer layer, irradiating a flash light beam onto the pattern mask from a plurality of flash lamps, and transferring the transfer layer to the acceptor substrate. The plurality of flash lamps are symmetrically provided with respect to the acceptor substrate and are configured to irradiate flash light beams.
Abstract:
A thin film transistor substrate may include a gate electrode on a base substrate, a gate insulation layer covering the gate electrode on the base substrate, an active pattern on the gate insulation layer, an etch-stop layer pattern partially exposing the active pattern, a source electrode and a drain electrode in contact with a portion of the exposed active pattern, and an inorganic barrier layer on the source electrode, the drain electrode, and the etch-stop layer pattern. The active pattern may be superimposed over the gate electrode. The source electrode and the drain electrode may be superimposed over both ends of the gate electrode. The inorganic barrier layer may be in contact with a remaining portion of the exposed active pattern.
Abstract:
A thermal treatment method for a display apparatus includes providing an acceptor substrate on a substrate stage, providing on the acceptor substrate a pattern mask including a transfer layer, irradiating a flash light beam onto the pattern mask from a plurality of flash lamps, and transferring the transfer layer to the acceptor substrate. The plurality of flash lamps are symmetrically provided with respect to the acceptor substrate and are configured to irradiate flash light beams.
Abstract:
A display substrate, method of manufacturing the same, and a display device including the same are disclosed. In one aspect, a display substrate includes a first gate electrode formed on a base substrate, a scan line electrically connected to the first gate electrode, a gate insulation layer, an etch stop layer and a passivation layer formed on the base substrate to at least partially overlap the first gate electrode and the scan line, and a data line formed on the passivation layer to at least partially overlap the scan line.