公开(公告)号：US20240234662A1

公开(公告)日：2024-07-11

申请号：US18453082

申请日：2023-08-21

Applicant: Samsung Display Co., LTD.

Inventor： JAEHYUN LEE ,  WOOGEUN LEE ,  KAP SOO YOON ,  HYUNGJIN SONG ,  JUNG KYOUNG CHO ,  SEUNG-HA CHOI

IPC: H01L33/62 ,  G09G3/32 ,  H01L25/075 ,  H01L25/16 ,  H01L27/12

CPC classification number: H01L33/62 ,  G09G3/32 ,  H01L25/0753 ,  H01L25/167 ,  H01L27/124 ,  H01L27/1255 ,  G09G2310/0267

Abstract: A display device includes: a substrate; a first conductive layer on the substrate and including a lower conductive pattern and a capacitor conductive pattern spaced apart from the lower conductive pattern in a plan view; an active layer on the first conductive layer, partially overlapping the lower conductive pattern and the capacitor conductive pattern in the plan view, and including a driving active pattern defining a storage capacitor together with the capacitor conductive pattern; a second conductive layer on the active layer, partially overlapping the lower conductive pattern and the driving active pattern in the plan view, and including a control pattern defining a driving transistor together with the driving active pattern; and a third conductive layer on the second conductive layer and including an anode electrode partially overlapping the lower conductive pattern in the plan view.

公开(公告)号：US20240016002A1

公开(公告)日：2024-01-11

申请号：US18317963

申请日：2023-05-16

Applicant: Samsung Display Co., Ltd.

Inventor： HYUN KIM ,  SEUL-KI KIM ,  SEUNG-HA CHOI ,  KAP SOO YOON ,  WOOGEUN LEE ,  YEEUN KANG ,  JUNG KYOUNG CHO

IPC: H10K59/121 ,  H10K59/122 ,  H10K59/80

CPC classification number: H10K59/1213 ,  H10K59/122 ,  H10K59/80521 ,  H10K59/80515

Abstract: A display device includes a base substrate, a circuit layer including a transistor including a gate electrode, an auxiliary conductive layer, a first insulating layer disposed on the transistor and the auxiliary conductive layer, and a second insulating layer disposed on the first insulating layer, and a display element layer including a pixel defining layer disposed on the circuit layer and a light-emitting element including a first electrode, a functional layer, and a second electrode, which are sequentially stacked.

公开(公告)号：US20240065045A1

公开(公告)日：2024-02-22

申请号：US18124604

申请日：2023-03-22

Applicant: Samsung Display Co., Ltd.

Inventor： HYUN KIM ,  SHOYEON KIM ,  SEUL-KI KIM ,  KAP SOO YOON ,  JAEHYUN LEE ,  SEUNG-HA CHOI

IPC: H10K59/124 ,  H10K59/12

CPC classification number: H10K59/124 ,  H10K59/1201

Abstract: A display panel includes a base substrate, a transistor disposed on the base substrate and including a semiconductor pattern including a source area, a drain area, and an active area, a gate insulating pattern layer disposed on the semiconductor pattern, and a gate electrode disposed on the gate insulating pattern, and connection electrodes disposed on the gate insulating pattern layer and connected to the semiconductor pattern through contact holes, respectively. The gate insulating pattern layer includes a first portion overlapping at least one of the source area and the drain area and a second portion extending from the first portion. A thickness of the first portion is equal to or smaller than about 50% of a thickness of the second portion.

公开(公告)号：US20230128398A1

公开(公告)日：2023-04-27

申请号：US17874702

申请日：2022-07-27

Applicant: Samsung Display Co., Ltd.

Inventor： JAEHYUN LEE ,  SEUL-KI KIM ,  KAP SOO YOON ,  KI SU JIN ,  SEUNG-HA CHOI ,  JONGBUM CHOI

IPC: H01L27/32 ,  H01L51/56

Abstract: A display device includes a pixel, a first pad electrode disposed around the pixel, a buffer layer disposed on the first pad electrode, a first insulating layer disposed on the buffer layer, and a second pad electrode disposed on the first insulating layer, the second pad electrode being electrically connected to the first pad electrode through a contact hole in the first insulating layer and the buffer layer. A first step, a second step below the first step, and a third step below the second step are defined on the first insulating layer and the buffer layer around the first pad electrode and the second pad electrode.

公开(公告)号：US20160181284A1

公开(公告)日：2016-06-23

申请号：US15053807

申请日：2016-02-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： SHO YEON KIM ,  HYUN KIM ,  EUN HYE PARK ,  BYUNG HWAN CHU ,  SEUNG-HA CHOI

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a first connection member of a gate driver region and a gate electrode of a display area, a gate insulating layer disposed on the substrate and having a first contact hole exposing the first connection member, a semiconductor layer disposed on a region of the gate insulating layer, a data line disposed on the gate insulating layer and the semiconductor layer and including a drain electrode, a source electrode, and a second connection member connected to the first connection member through the first contact hole, a passivation layer disposed on the data line, the source electrode, the drain electrode, and the second connection member, and a pixel electrode disposed on the passivation layer and electrically connected to the drain electrode. A horizontal width of the first contact hole ranges from 1 to 2 μm.

公开(公告)号：US20150200209A1

公开(公告)日：2015-07-16

申请号：US14486620

申请日：2014-09-15

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： SHO YEON KIM ,  HYUN KIM ,  EUN HYE PARK ,  BYUNG HWAN CHU ,  SEUNG-HA CHOI

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a first connection member of a gate driver region and a gate electrode of a display area, a gate insulating layer disposed on the substrate and having a first contact hole exposing the first connection member, a semiconductor layer disposed on a region of the gate insulating layer, a data line disposed on the gate insulating layer and the semiconductor layer and including a drain electrode, a source electrode, and a second connection member connected to the first connection member through the first contact hole, a passivation layer disposed on the data line, the source electrode, the drain electrode, and the second connection member, and a pixel electrode disposed on the passivation layer and electrically connected to the drain electrode. A horizontal width of the first contact hole ranges from 1 to 2 μm.

Abstract translation: 薄膜晶体管阵列面板包括：栅极线，其设置在基板上，并且包括栅极驱动器区域的第一连接构件和显示区域的栅极电极，栅极绝缘层，设置在所述基板上，并且具有暴露于所述第一接触孔 所述第一连接构件，设置在所述栅极绝缘层的区域上的半导体层，设置在所述栅极绝缘层和所述半导体层上的数据线，并且包括漏电极，源电极和连接到所述第一连接构件的第二连接构件 连接构件，通过第一接触孔，设置在数据线上的钝化层，源电极，漏电极和第二连接构件，以及设置在钝化层上并电连接到漏电极的像素电极。 第一接触孔的水平宽度为1〜2μm。