公开(公告)号：US20250079302A1

公开(公告)日：2025-03-06

申请号：US18444990

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungjae BAE ,  Jin-Wook YANG ,  Seung Pil KO ,  Yongjae KIM ,  Junho PARK ,  Kilho LEE

IPC: H01L23/528 ,  H01L23/48 ,  H01L29/417 ,  H10B61/00

Abstract: A semiconductor device includes a substrate having a top surface and a bottom surface opposite to each other, a gate structure on the top surface of the substrate, a plurality of source/drain patterns on the top surface of the substrate and on opposite sides of the gate structure, a backside conductive line on the bottom surface of the substrate and electrically connected to at least one of the gate structure or a first source/drain pattern of the source/drain patterns, and a magnetic tunnel junction pattern electrically connected to a second source/drain pattern of the source/drain patterns.

公开(公告)号：US20240164220A1

公开(公告)日：2024-05-16

申请号：US18384404

申请日：2023-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungjong JEONG ,  Seungpil KO ,  Byoungjae BAE ,  Manjin EOM ,  Gawon LEE ,  Kuhoon CHUNG

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10B61/20 ,  H10N50/10 ,  H10N50/01

Abstract: A magnetoresistive random access memory device includes a substrate; conductive patterns on the substrate; an insulating interlayer covering the conductive patterns; a lower electrode contact passing through the insulating interlayer, the lower electrode contact contacting the conductive pattern; a lower electrode on the lower electrode contact, the lower electrode including a rounded sidewall; and a memory structure on the lower electrode, the memory structure including a stacked MTJ structure and upper electrode, wherein a width of the lower electrode increases from a lower portion to an upper portion, the memory structure has a sidewall slope such that a width of the memory structure increases from an upper portion to a lower portion, and at least a portion of a sidewall of the lower electrode is covered by the first insulating interlayer.

公开(公告)号：US20240074208A1

公开(公告)日：2024-02-29

申请号：US18300021

申请日：2023-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungjae BAE ,  Seungpil Ko ,  Inho Kim ,  Hyungjiong Jeong

IPC: H10B61/00

CPC classification number: H10B61/00

Abstract: A semiconductor device includes an etch stop layer, an insulating layer on the etch stop layer, and a contact structure passing through the etch stop layer and the insulating layer, the contact structure including a first conductive layer, a second conductive layer having a side surface and a lower surface facing the first conductive layer, a third conductive layer on an upper surface of the second conductive layer, and a natural oxide film between the first conductive layer and the second conductive layer and between the second conductive layer and the third conductive layer, the first to third conductive layers including metal or metal nitride, and the natural oxide film including metal oxide.

公开(公告)号：US20240324240A1

公开(公告)日：2024-09-26

申请号：US18478318

申请日：2023-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjong JEONG ,  Seung Pil KO ,  Kyounghun RYU ,  Byoungjae BAE ,  Kwangil SHIN

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/20

CPC classification number: H10B61/00 ,  H10N50/01 ,  H10N50/20

Abstract: A magnetic memory device may include a substrate, a lower interconnection line on the substrate, a data storage structure on the lower interconnection line, and a lower contact plug between the lower interconnection line and the data storage structure and extended in a first direction perpendicular to a top surface of the substrate to connect the lower interconnection line to the data storage structure. An upper portion of the lower contact plug may have a first width in a second direction parallel to the top surface of the substrate, and a lower portion of the lower contact plug may have a second width in the second direction. The first width may be larger than the second width.

公开(公告)号：US20230139618A1

公开(公告)日：2023-05-04

申请号：US17862831

申请日：2022-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungjae BAE ,  Shin KWON ,  Jeongmin PARK ,  Manjin EOM ,  Hyungjong JEONG

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, interconnection lines on the cell region and the peripheral region, the interconnection lines being spaced apart from the substrate in a first direction perpendicular to a top surface of the substrate, a lower insulating layer on the cell region and the peripheral region, the lower insulating layer covering the interconnection lines, and a top surface of the lower insulating layer on the cell region being at a lower height than top surfaces of uppermost interconnection lines of the interconnection lines, and data storage patterns on the lower insulating layer on the cell region, the data storage patterns being horizontally spaced apart from each other, and the data storage patterns being connected directly to the top surfaces of the uppermost interconnection lines on the cell region.