公开(公告)号：US20220328083A1

公开(公告)日：2022-10-13

申请号：US17537937

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Pil KO ,  Yongjae KIM ,  Geonhee BAE ,  Gawon LEE ,  Kilho LEE

IPC: G11C11/16 ,  H01L23/528 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22 ,  H01L43/02

Abstract: A magnetic memory device may include a substrate including a first region and a second region, a first interlayer insulating layer on the substrate, a first capping layer on the first interlayer insulating layer, the first capping layer covering the first and second regions of the substrate, a second interlayer insulating layer on a portion of the first capping layer covering the first region of the substrate, a bottom electrode contact included in the second interlayer insulating layer, a magnetic tunnel junction pattern on the bottom electrode contact, and a second capping layer on the second interlayer insulating layer, the second capping layer being in contact with the first capping layer on the second region of the substrate.

公开(公告)号：US20210005663A1

公开(公告)日：2021-01-07

申请号：US17027980

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoungsu SON ,  Seung Pil KO ,  Jung Hyuk LEE ,  Shinhee HAN ,  Gwan-Hyeob KOH ,  Yoonjong SONG

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08

Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

公开(公告)号：US20240324240A1

公开(公告)日：2024-09-26

申请号：US18478318

申请日：2023-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjong JEONG ,  Seung Pil KO ,  Kyounghun RYU ,  Byoungjae BAE ,  Kwangil SHIN

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/20

CPC classification number: H10B61/00 ,  H10N50/01 ,  H10N50/20

Abstract: A magnetic memory device may include a substrate, a lower interconnection line on the substrate, a data storage structure on the lower interconnection line, and a lower contact plug between the lower interconnection line and the data storage structure and extended in a first direction perpendicular to a top surface of the substrate to connect the lower interconnection line to the data storage structure. An upper portion of the lower contact plug may have a first width in a second direction parallel to the top surface of the substrate, and a lower portion of the lower contact plug may have a second width in the second direction. The first width may be larger than the second width.

公开(公告)号：US20240114700A1

公开(公告)日：2024-04-04

申请号：US18448615

申请日：2023-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongjae LEE ,  Seung Pil KO ,  Kilho LEE ,  Jeongjin LEE

IPC: H10B61/00 ,  H01L23/00 ,  H01L27/146 ,  H10B80/00

CPC classification number: H10B61/22 ,  H01L24/08 ,  H01L27/14634 ,  H10B80/00 ,  H01L2224/08145

Abstract: A semiconductor device includes cell lower conductive lines and peripheral lower conductive lines on a substrate, lower electrode contacts on the cell lower conductive lines, peripheral conductive contacts on the peripheral lower conductive lines, variable resistance patterns horizontally spaced apart from each other on the lower electrode contacts. The lower electrode contacts are respectively connected to the variable resistance patterns. Peripheral conductive lines are horizontally spaced apart from the variable resistance patterns on the peripheral conductive contacts. The peripheral conductive contacts are connected to the peripheral conductive lines. The cell and peripheral lower conductive lines are connected to the lower electrode contacts and the peripheral conductive contacts, respectively. The cell and peripheral lower conductive lines are at the same height. A pitch of the cell lower conductive lines directly adjacent to each other is greater than a pitch of the peripheral lower conductive lines directly adjacent to each other.

公开(公告)号：US20240365562A1

公开(公告)日：2024-10-31

申请号：US18510954

申请日：2023-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Hyuk LEE ,  Seung Pil KO

IPC: H10B61/00

CPC classification number: H10B61/00

Abstract: A semiconductor device may include a substrate including a cell region and a peripheral region, a bottom electrode overlapping the cell region, a magnetic tunnel junction pattern on the bottom electrode, a top electrode on the magnetic tunnel junction pattern, a buffer insulating layer overlapping the peripheral region, a capping insulating layer in contact with a side surface of the top electrode and a top surface of the buffer insulating layer, and a first peripheral conductive structure penetrating the capping insulating layer and the buffer insulating layer. A level difference between the top surface of the buffer insulating layer and a top surface of the top electrode may be smaller than a thickness of the capping insulating layer.

公开(公告)号：US20190326355A1

公开(公告)日：2019-10-24

申请号：US16161370

申请日：2018-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoungsu SON ,  Seung Pil KO ,  Jung Hyuk LEE ,  Shinhee HAN ,  Gwan-Hyeob KOH ,  Yoonjong SONG

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

公开(公告)号：US20250079302A1

公开(公告)日：2025-03-06

申请号：US18444990

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungjae BAE ,  Jin-Wook YANG ,  Seung Pil KO ,  Yongjae KIM ,  Junho PARK ,  Kilho LEE

IPC: H01L23/528 ,  H01L23/48 ,  H01L29/417 ,  H10B61/00

Abstract: A semiconductor device includes a substrate having a top surface and a bottom surface opposite to each other, a gate structure on the top surface of the substrate, a plurality of source/drain patterns on the top surface of the substrate and on opposite sides of the gate structure, a backside conductive line on the bottom surface of the substrate and electrically connected to at least one of the gate structure or a first source/drain pattern of the source/drain patterns, and a magnetic tunnel junction pattern electrically connected to a second source/drain pattern of the source/drain patterns.

公开(公告)号：US20210296397A1

公开(公告)日：2021-09-23

申请号：US17019641

申请日：2020-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Pil KO ,  Yongjae KIM

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: A method of fabricating a semiconductor device including providing a substrate; forming first and second lower conductive patterns, the and second lower conductive patterns being buried in an interlayer dielectric layer; forming a capping layer on the interlayer dielectric layer and a dummy layer on the capping layer; etching an exposed upper portion of the first lower conductive pattern to form a trench; forming a metal layer that covers the interlayer dielectric layer and the dummy layer such that the metal layer fills the trench; forming a magnetic tunnel junction layer on the metal layer; performing a patterning process to form a memory cell; and forming a first protective layer that covers a lateral surface of the memory cell, wherein, in the patterning process, the metal layer on the top surface of the interlayer dielectric layer is etched to form a first bottom electrode in the trench.

公开(公告)号：US20190088656A1

公开(公告)日：2019-03-21

申请号：US15959366

申请日：2018-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong Hyun KIM ,  Seung Pil KO ,  Hyunchul SHIN ,  Kilho LEE

IPC: H01L27/105 ,  G11C11/16 ,  H01L43/02

Abstract: Disclosed are data storage devices and methods of manufacturing the same. The methods may include providing a substrate including a cell region and a peripheral circuit region, forming a data storage layer on the cell region and the peripheral circuit region of the substrate, selectively forming a mask layer on a portion of the data storage layer that is formed on the peripheral circuit region, forming a top electrode layer on the data storage layer and the mask layer, patterning the top electrode layer to form a plurality of top electrodes on the cell region, and patterning the data storage layer using the plurality of top electrodes as an etch mask to form a plurality of data storage parts on the cell region. While patterning the top electrode layer, the mask layer on the peripheral circuit region may serve as an etch stop layer.

公开(公告)号：US20180350875A1

公开(公告)日：2018-12-06

申请号：US15791503

申请日：2017-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonsung HAN ,  Seung Pil KO

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a substrate including a cell region and a peripheral region, a magnetic tunnel junction pattern on the cell region, a capping insulation layer covering a sidewall of the magnetic tunnel junction pattern, and an upper insulation layer including a first portion on the capping insulation layer and a second portion on the peripheral region. A level of a bottom surface of the second portion is lower than that of a bottom surface of the capping insulation layer.