Abstract:
An artificial intelligence calculation semiconductor device is provided. The artificial intelligence calculation semiconductor device comprising: a control unit; and a MAC (Multiply and Accumulator) calculator which executes a homomorphic encryption calculation through the control unit, wherein the MAC calculator includes an NTT (Numeric Theoretic Transform)/INTT (Inverse NTT) circuit which generates cipher texts by performing a homomorphic multiplication calculation through transformation or inverse transformation of data, a cipher text multiplier which executes a multiplication calculation between the cipher texts, a cipher text adder/subtractor which executes addition and/or subtraction calculations between the cipher texts, and a rotator which performs a cyclic shift of a slot of the cipher texts.
Abstract:
Provided are a data receiving device and a corresponding method for receiving the data. The data receiving device comprises a path control logic configured to store L symbol paths, where L is a natural number equal to or greater than 2, L feedback filters configured to calculate L inter-symbol interferences (ISI) for the L symbol paths, respectively, L operators configured to remove the L inter-symbol interferences from an output of a feed-forward equalizer, and a path metric calculator configured to receive outputs of the L operators and calculate a path metric for each of the L symbol paths, wherein the path control logic is configured to select L values among the calculated path metrics for the L symbol paths to update the L symbol paths.
Abstract:
A storage device is provided including an interface circuit configured to receive application information from a host; a field programmable gate array (FPGA); a neural processing unit (NPU); and a central processing unit (CPU) configured to select a hardware image from among a plurality of hardware images stored in a memory using the application information, and reconfigure the FPGA using the selected hardware image. The NPU is configured to perform an operation using the reconfigured FPGA.
Abstract:
A memory controller controls operation of a nonvolatile memory device comprising a memory area comprising a plurality of multi-level cells (MLCs). The memory controller receives an address of the memory area and data to be programmed to the memory area, analyzes access history information regarding the memory area based on the address, generates first mapping data corresponding to the data or second mapping data based on the data and previous mapping data that has been programmed to the MLCs according to a result of the analysis, and transmits a program command comprising one of the first mapping data and the second mapping data to the nonvolatile memory device.
Abstract:
A signal processing method of a semiconductor device, the method including: receiving a first digital code of a first digital signal; generating a constraint vector; masking the first digital code with a transmitting mask based on the constraint vector; and outputting the masked first digital code and a Data Bus Inversion (DBI) bit of the mask.
Abstract:
A data transmission method for transmitting a data signal using four data signal levels during a unit interval and transmitting a data bus inversion (DBI) signal using two DBI signal levels during the unit interval, the method including: receiving n (n is a natural number) data, each of the n data including a first bit and a second bit; counting the number of data in which the first bit and the second bit have the same value among the n data; in response to the counting result being less than or equal to a predetermined number, transmitting the n data using the four data signal levels, together with a DBI signal having a first DBI signal level; and in response to the counting result being greater than the predetermined number, transmitting data, which is obtained by changing a value of either of the first bit and the second bit of the n data, using the four data signal levels, together with a DBI signal having a second DBI signal level different from the first DBI signal level.
Abstract:
A data transmission method for transmitting a data signal using four data signal levels during a unit interval and transmitting a data bus inversion (DBI) signal using two DBI signal levels during the unit interval, the method including: receiving n (n is a natural number) data, each of the n data including a first bit and a second bit; counting the number of data in which the first bit and the second bit have the same value among the n data; in response to the counting result being less than or equal to a predetermined number, transmitting the n data using the four data signal levels, together with a DBI signal having a first DBI signal level; and in response to the counting result being greater than the predetermined number, transmitting data, which is obtained by changing a value of either of the first bit and the second bit of the n data, using the four data signal levels, together with a DBI signal having a second DBI signal level different from the first DBI signal level.
Abstract:
A method of processing data using a memory controller includes determining at least one cell state to which each of a plurality of multi-level cells can be changed to based on a current cell state of each multi-level cell, where each multi-level cell includes a plurality of data pages; determining one of the data pages as having a stuck bit when a value of the data page has a single mapping value based on mapping values mapped to the at least one cell state and generating stuck bit data regarding the stuck bit; and encoding write data to be stored in the multi-level cells based on the stuck bit data.
Abstract:
Provided are a data receiving device and a corresponding method for receiving the data. The data receiving device comprises a path control logic configured to store L symbol paths, where L is a natural number equal to or greater than 2, L feedback filters configured to calculate L inter-symbol interferences (ISI) for the L symbol paths, respectively, L operators configured to remove the L inter-symbol interferences from an output of a feed-forward equalizer, and a path metric calculator configured to receive outputs of the L operators and calculate a path metric for each of the L symbol paths, wherein the path control logic is configured to select L values among the calculated path metrics for the L symbol paths to update the L symbol paths.
Abstract:
A method of operating a memory controller includes receiving a first data sequence and generating a coset representative sequence that can be divided into m-bit strings, where “m” is a natural number of at least 2; performing a first XOR operation on each of the m-bit strings in the coset representative sequence and binary bits; calculating all possible branch metrics according to a result of the first XOR operation; determining a survivor path sequence based on the all possible branch metrics; and performing a second XOR operation on the coset representative sequence and the survivor path sequence and generating an output sequence.