公开(公告)号：US12158772B2

公开(公告)日：2024-12-03

申请号：US18170747

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongun Jeong ,  Donghyeok Jeong ,  ChangSik Yoo ,  Kihan Kim

IPC: G06F1/12

Abstract: Disclosed is a clock multiplexing circuit which includes a first transistor that is between a first input terminal that receives a first input clock signal and an output terminal that outputs an output pulse signal and operates based on a logic level of a second input terminal receiving a second input clock signal, and a second transistor that is between the output terminal and a first voltage node and operates based on the logic level of the second input terminal. The first input clock signal and the second input clock signal have the same period and have different phases. The output pulse signal transitions to a first logic level at a first time when the first input clock signal transitions to the first logic level and transitions to a second logic level at a second time when the second input clock signal transitions to the first logic level.

公开(公告)号：US20230377667A1

公开(公告)日：2023-11-23

申请号：US18319584

申请日：2023-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewoo Lee ,  Yonghun Kim ,  Kihan Kim ,  ChangSik Yoo

IPC: G11C29/12 ,  G11C29/36

CPC classification number: G11C29/12015 ,  G11C29/36 ,  G11C29/1201

Abstract: A semiconductor device includes: a data clock signal generator circuit configured to output a plurality of data clock signals that have different phases and that are used to generate a plurality of internal data clock signals of a memory device; a data transmitter configured to generate a data signal based on a test pattern transitioned once, delay the data signal once transitioned according to a delay value, and output the data signal to the memory device; a data receiver configured to receive an output signal from the memory device that includes first sampling data, the first sampling data being obtained by sampling the data signal based on a first internal data clock signal from the plurality of internal data clock signals; and a training circuit configured to change the delay value and determine a final value of the delay value based on the first sampling data.

公开(公告)号：US20250078906A1

公开(公告)日：2025-03-06

申请号：US18818007

申请日：2024-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Heung Kim ,  ChangSik Yoo ,  Jeongdon Ihm ,  Hyongryol Hwang

IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory device includes a bank array including a plurality of memory cells, a row decoder connected to the bank array through a plurality of wordlines, and a column decoder connected to the bank array through a plurality of column select lines. The bank array may include a first region and a second region different from the first region. First metadata for first normal data stored in the first region is stored in the second region, and second metadata for second normal data stored in the second region is stored in the first region.

公开(公告)号：US20230377621A1

公开(公告)日：2023-11-23

申请号：US18189580

申请日：2023-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewoo Lee ,  Yonghun Kim ,  Kihan Kim ,  ChangSik Yoo

IPC: G11C7/22 ,  G11C7/10 ,  G11C29/02

CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C29/023 ,  G11C7/1093 ,  G11C2207/2254

Abstract: A semiconductor device includes: a clock generation circuit configured to output a plurality of clock signals that have different phases to a memory device, an internal clock signal of the memory device being generated responsive to the plurality of clock signals; and a training circuit configured to receive an output signal output based on the internal clock signal from the memory device, to adjust a value of a code used to generate the internal clock signal by adjusting the phase of at least one clock signal among the plurality of clock signals, to determine a final value of the code based on a duty cycle of the output signal, which is changed according to the adjustment of the value of the code, and to write the final value to the memory device.

公开(公告)号：US20250061939A1

公开(公告)日：2025-02-20

申请号：US18806022

申请日：2024-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Heung Kim ,  ChangSik Yoo ,  Jeongdon Ihm ,  Hyongryol Hwang

IPC: G11C11/4096 ,  G11C11/408

Abstract: A memory device includes at least one bank including a first sub-bank and a second sub-bank disposed in a wordline direction. The first sub-bank may store normal data and may be connected to a plurality of first wordlines, the second sub-bank may store metadata corresponding to the normal data and may be connected to a plurality of second wordlines, and metadata for normal data corresponding to each of the first wordlines may be stored in each of second wordlines, respectively corresponding to the first wordlines.

公开(公告)号：US20240028065A1

公开(公告)日：2024-01-25

申请号：US18170747

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongun Jeong ,  Donghyeok Jeong ,  ChangSik Yoo ,  Kihan Kim

IPC: G06F1/12

CPC classification number: G06F1/12

Abstract: Disclosed is a clock multiplexing circuit which includes a first transistor that is between a first input terminal that receives a first input clock signal and an output terminal that outputs an output pulse signal and operates based on a logic level of a second input terminal receiving a second input clock signal, and a second transistor that is between the output terminal and a first voltage node and operates based on the logic level of the second input terminal. The first input clock signal and the second input clock signal have the same period and have different phases. The output pulse signal transitions to a first logic level at a first time when the first input clock signal transitions to the first logic level and transitions to a second logic level at a second time when the second input clock signal transitions to the first logic level.

公开(公告)号：US20250060886A1

公开(公告)日：2025-02-20

申请号：US18805709

申请日：2024-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Heung Kim ,  ChangSik Yoo ,  Jeongdon Ihm ,  Hyongryol Hwang

IPC: G06F3/06

Abstract: A memory device includes at least one bank including at least a first sub-bank and a second sub-bank disposed in a wordline direction. The first sub-bank may include a normal data region connected to a plurality of first wordlines and storing normal data, the second sub-bank may include a metadata region connected to a plurality of second wordlines and storing metadata corresponding to the normal data, the plurality of first wordlines may match the plurality of second wordlines to form a plurality of wordline pairs, and the first sub-bank and the second sub-bank may share a row hammer region storing a number of access times to the plurality of wordline pairs.

公开(公告)号：US20250044828A1

公开(公告)日：2025-02-06

申请号：US18922797

申请日：2024-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongun Jeong ,  Donghyeok Jeong ,  ChangSik Yoo ,  Kihan Kim

IPC: G06F1/12

Abstract: Disclosed is a clock multiplexing circuit which includes a first transistor that is between a first input terminal that receives a first input clock signal and an output terminal that outputs an output pulse signal and operates based on a logic level of a second input terminal receiving a second input clock signal, and a second transistor that is between the output terminal and a first voltage node and operates based on the logic level of the second input terminal. The first input clock signal and the second input clock signal have the same period and have different phases. The output pulse signal transitions to a first logic level at a first time when the first input clock signal transitions to the first logic level and transitions to a second logic level at a second time when the second input clock signal transitions to the first logic level.