公开(公告)号：US20220130970A1

公开(公告)日：2022-04-28

申请号：US17367988

申请日：2021-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Won KANG ,  Tae-Yeol KIM ,  Jeong Ik KIM ,  Rak Hwan KIM ,  Jun Ki PARK ,  Chung Hwan SHIN

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.

公开(公告)号：US20250072096A1

公开(公告)日：2025-02-27

申请号：US18606375

申请日：2024-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi Woong SHIM ,  Seong Heum CHOI ,  Do Sun LEE ,  Hyo Seok CHOI ,  Rak Hwan KIM ,  Chung Hwan SHIN

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/768 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method of fabricating a semiconductor device includes: forming an active pattern on a substrate, forming a source/drain pattern on the active pattern, forming a contact hole on the source/drain pattern, forming a contact barrier layer, which has an upper surface of a first height based on a bottom surface of the contact hole, in the contact hole, forming a passivation layer on the contact barrier layer in the contact hole, forming a mask layer on the passivation layer in the contact hole, removing an upper portion of the contact barrier layer so that an upper surface of the contact barrier layer has a second height lower than the first height, removing the passivation layer and the mask layer, and forming a contact filling layer, which covers the upper surface of the contact barrier layer and fills the contact hole, in the contact hole.

公开(公告)号：US20240405090A1

公开(公告)日：2024-12-05

申请号：US18390782

申请日：2023-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong Heum CHOI ,  Jeong Hoon SEO ,  Rak Hwan KIM ,  Chung Hwan SHIN ,  Do Sun LEE

IPC: H01L29/45 ,  H01L21/285 ,  H01L29/40

Abstract: A semiconductor device is provided. The semiconductor device includes: a semiconductor device including: an active pattern extending in a first direction; a gate structure including a gate electrode extending in a second direction and a gate spacer on the active pattern, wherein the gate electrode and the gate spacer are spaced apart from each other in the first direction; a source/drain pattern on the active pattern; a contact barrier layer on the source/drain pattern; and a contact filling layer on the contact barrier layer. An uppermost point of the contact barrier layer is between an upper surface of the contact filling layer and a lower surface of the contact filling layer, and outer walls of the contact barrier layer and outer walls of the contact filling layer extend along a common plane.

公开(公告)号：US20240332381A1

公开(公告)日：2024-10-03

申请号：US18382395

申请日：2023-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Won KANG ,  Chung Hwan SHIN ,  Seong Heum CHOI ,  Rak Hwan KIM

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/775 ,  H01L29/7851

Abstract: A semiconductor device may include an active pattern extending in a first direction, a gate structure which is placed on the active pattern to be spaced apart from each other in the first direction, and includes a gate electrode and a gate spacer, the gate electrode extending in a second direction intersecting the first direction, a gate contact on the gate structure, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a via plug on the source/drain contact. An upper surface of the gate contact and a second upper surface of the via plug may be placed on the same plane. A lower surface of the gate contact and a lower surface of the via plug may be different in height, on the basis of an upper surface of the active pattern.

公开(公告)号：US20220319916A1

公开(公告)日：2022-10-06

申请号：US17838740

申请日：2022-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won Keun CHUNG ,  Joon Gon LEE ,  Rak Hwan KIM ,  Chung Hwan SHIN ,  Do Sun LEE ,  Nam Gyu CHO

IPC: H01L21/768

Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.