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公开(公告)号:US20210242320A1
公开(公告)日:2021-08-05
申请号:US17222474
申请日:2021-04-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Junghwan HUH , Dongchan KIM , Dae Hyun KIM , Euiju KIM , Jisoo LEE
IPC: H01L29/423 , H01L29/78 , H01L29/51 , H01L29/49
Abstract: A semiconductor device includes a substrate including an active region, a gate trench disposed in the substrate and crossing the active region; a gate dielectric layer disposed in the gate trench; a first gate electrode disposed on the gate dielectric layer and including center and edge portions; a second gate electrode disposed on the first gate electrode; a gate capping insulating layer disposed on the second gate electrode and filling the gate trench; and first and second impurity regions disposed in the substrate opposite to each other with respect to the gate trench. A top surface of each of the center and edge portions contacts a bottom surface of the second gate electrode. The top surface of the second gate electrode is concave. The bottom surface of the gate capping insulating layer is convex, and a side surface of the gate capping insulating layer contacts the gate dielectric layer.
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公开(公告)号:US20210004289A1
公开(公告)日:2021-01-07
申请号:US17029912
申请日:2020-09-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Myung Kyu LEE , Jun Jin KONG , Ki Jun LEE , Sung Hye CHO , Dae Hyun KIM , Yong Gyu CHU
Abstract: Disclosed are a semiconductor memory device, a controller, a memory system, and an operation method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.
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公开(公告)号:US20200133768A1
公开(公告)日:2020-04-30
申请号:US16372047
申请日:2019-04-01
Applicant: Samsung Electronics Co., Ltd.
Inventor: Myung Kyu LEE , Jun Jin KONG , Ki Jun LEE , Sung Hye CHO , Dae Hyun KIM , Yong Gyu CHU
Abstract: Disclosed are a semiconductor memory device, a controller, and a memory system. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.
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公开(公告)号:US20200152753A1
公开(公告)日:2020-05-14
申请号:US16523529
申请日:2019-07-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Junghwan HUH , Dongchan KIM , Dae Hyun KIM , Euiju KIM , Jisoo LEE
IPC: H01L29/423 , H01L29/78 , H01L29/49 , H01L29/51
Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate trench crossing an active region, and a gate structure in the gate trench. The gate structure includes a gate dielectric layer disposed on an inner wall of the gate trench, a gate electrode disposed on the gate electric layer and partially filling the gate trench, a gate capping insulating layer disposed on the gate electrode, and a gap-fill insulating layer disposed in the gate trench and disposed on the gate capping insulating layer. The gate capping insulating layer includes a material formed by oxidizing a portion of the gate electrode, nitriding the portion of the gate electrode, or oxidizing and nitriding the portion of the gate electrode.
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公开(公告)号:US20130194790A1
公开(公告)日:2013-08-01
申请号:US13781037
申请日:2013-02-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Young Sam PARK , Hun Joo HAHM , Hyung Suk KIM , Seong Yeon HAN , Dae Hyun KIM , Do Hun KIM , Dae Yeon KIM
IPC: F21V21/005 , F21V13/08 , F21V29/00 , F21V9/16 , F21V13/02
CPC classification number: F21V21/005 , F21K9/00 , F21V13/02 , F21V13/08 , F21V23/06 , F21Y2103/10 , F21Y2115/10 , H01L2224/48091 , H01L2924/181 , H05K1/142 , H05K3/0061 , H05K2201/10106 , H05K2201/10189 , H05K2201/10446 , Y10S362/80 , H01L2924/00014 , H01L2924/00012
Abstract: There is provided a light emitting module including: a printed circuit board; a plurality of light emitting diode chips disposed at a distance from one another on a conductive pattern formed on a top of the printed circuit board; and a connector formed on a bottom of the printed circuit board and electrically connected to the plurality of light emitting diode chips. The light emitting diode chips and the connector are optimally arranged to ensure that the light emitting module is suitably utilized as a high-density linear light source including a great number of light emitting diode chips and emits light outward with minimum loss.
Abstract translation: 提供了一种发光模块,包括:印刷电路板; 在形成在印刷电路板的顶部上的导电图案上彼此间隔一定距离设置的多个发光二极管芯片; 以及形成在印刷电路板的底部并且电连接到多个发光二极管芯片的连接器。 最优地布置发光二极管芯片和连接器,以确保发光模块适合用作包括大量发光二极管芯片的高密度线性光源,并以最小的损耗向外发光。
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公开(公告)号:US20240213342A1
公开(公告)日:2024-06-27
申请号:US18599522
申请日:2024-03-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Junghwan HUH , Dongchan KIM , Dae Hyun KIM , Euiju KIM , Jisoo LEE
IPC: H01L29/423 , H01L21/768 , H01L21/8234 , H01L29/49 , H01L29/51 , H01L29/78
CPC classification number: H01L29/4236 , H01L21/76877 , H01L21/823437 , H01L21/82345 , H01L29/42364 , H01L29/4916 , H01L29/518 , H01L29/78 , H01L29/7827
Abstract: A semiconductor device includes a substrate, a gate trench in the substrate, a gate insulating film in the gate trench, a titanium nitride (TiN)-lower gate electrode film on the gate insulating film, the titanium nitride (TiN)-lower gate electrode film including a top surface, a first side surface, and a second side surface opposite the first side surface, a polysilicon-upper gate electrode film on the titanium nitride (TiN)-lower gate electrode film, and a gate capping film on the polysilicon-upper gate electrode film. A center portion of the top surface of the titanium nitride (TiN)-lower gate electrode film overlaps a center portion of the polysilicon-upper gate electrode film in a direction that is perpendicular to a top surface of the substrate, and each of the first side surface and the second side surface of the titanium nitride (TiN)-lower gate electrode film is connected to the gate insulating film.
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公开(公告)号:US20230342113A1
公开(公告)日:2023-10-26
申请号:US18342385
申请日:2023-06-27
Applicant: Samsung Electronics Co., Ltd.
Inventor: Young Nam HWANG , Hyung-Dal KWON , Dae Hyun KIM
CPC classification number: G06F7/5443 , G06F17/15 , G06N3/063
Abstract: Provided is a neural processing unit that performs application-work including a first neural network operation, the neural processing unit includes a first processing core configured to execute the first neural network operation, a hardware block reconfigurable as a hardware core configured to perform hardware block-work, and at least one processor configured to execute computer-readable instructions to distribute a part of the application-work as the hardware block-work to the hardware block based on a first workload of the first processing core.
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