公开(公告)号：US20240120921A1

公开(公告)日：2024-04-11

申请号：US18390224

申请日：2023-12-20

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Daehyun KWON ,  Hyejung KWON ,  Hyeran KIM ,  Chisung OH

IPC: H03K19/017 ,  H03K19/00 ,  H03K19/17736 ,  H03K19/17772

CPC classification number: H03K19/01742 ,  H03K19/0005 ,  H03K19/1774 ,  H03K19/17772

Abstract: An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

公开(公告)号：US20240386921A1

公开(公告)日：2024-11-21

申请号：US18413180

申请日：2024-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Kwan PARK ,  Daehyun KWON ,  JANG HOO KIM ,  CHANG-HYUN BAE ,  YOO-CHANG SUNG ,  HYE-SEUNG YU

IPC: G11C7/10 ,  H03K19/00

Abstract: A memory module includes a plurality of memory devices. Each of the plurality of memory devices includes a plurality of data input/output pads, a plurality of on-die termination (ODT) circuits each including one or more resistors, a plurality of transceiver circuits each including one or more transmission drivers and one or more reception buffers, and a plurality of equalizer circuits each including one or more inductors. Each of the plurality of equalizer circuits is connected to one of the plurality of data input/output pads, one of the plurality of ODT circuits, and one of the plurality of transceiver circuits. Each of the one or more transmission drivers drives a node of one of the plurality of data input/output pads. Inductances of the one or more inductors have individual values which are based on a driver strength of each of the one or more transmission drivers.

公开(公告)号：US20220321125A1

公开(公告)日：2022-10-06

申请号：US17591093

申请日：2022-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daehyun KWON ,  Hyejung KWON ,  Hyeran KIM ,  Chisung OH

IPC: H03K19/017 ,  H03K19/00 ,  H03K19/17772 ,  H03K19/17736

Abstract: An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

公开(公告)号：US20250087293A1

公开(公告)日：2025-03-13

申请号：US18883687

申请日：2024-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINSEONG YUN ,  Daehyun KWON ,  KI-HEUNG KIM ,  JONGHOON KIM ,  Sunghak LEE ,  CHANG-YONG LEE

IPC: G11C29/56

Abstract: A memory module includes: a circuit board including a plurality of signal lines to which a command is applied; and a first memory device mounted on a first surface of the circuit board, connected to the plurality of signal lines, including a first mode register, and configured to: operate in a standard mode or a mirrored mode, based on a value set in the first mode register, set a value corresponding to the mirrored mode in the first mode register, based on a first command applied to the plurality of signal lines, wherein at least one bit of a plurality of command/address bits in the first command is swapped with at least one bit of a plurality of command/address bits in a second command.

公开(公告)号：US20230186958A1

公开(公告)日：2023-06-15

申请号：US17903578

申请日：2022-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyeok BAEK ,  Daehyun KWON ,  Hyejung KWON ,  Donggun AN ,  Daewoong LEE

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C2207/2254

Abstract: A calibration circuit includes a first, second and third pull-up units each connected to a first power supply node, and first and second pull-down units each connected to a second power supply node. A first code generator is configured to generate a first code by comparing a voltage of a pad at which the first pull-up unit is connected to an external resistor with a reference voltage, and a second code generator is configured to generate a second code by comparing a voltage of a first intermediate node with the reference voltage and output the second code to the first and second pull-down units. A third code generator is configured to generate a third code by comparing a voltage of a second intermediate node between the second pull-down unit and the third pull-up unit with the reference voltage.