公开(公告)号：US20230048180A1

公开(公告)日：2023-02-16

申请号：US17872634

申请日：2022-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Segab Kwon ,  Hyoshin Ahn ,  Daesin Kim ,  Inkook Jang

IPC: H01L27/24

Abstract: A memory device includes a plurality of first conductive lines on a substrate and extending in a first direction, a plurality of second conductive lines on the plurality of first conductive lines and extending in a second direction intersecting the first direction, and a plurality of memory cells respectively between the plurality of first conductive lines and the plurality of second conductive lines. Each of the plurality of memory cells includes a switching element and a variable resistance material layer. The switching element includes a material having a composition of [GeX PY SeZ](1-W) [O]W, where 0.15≤X≤0.50, 0.15≤Y≤0.50, 0.35≤Z≤0.70, and 0.01≤W≤0.10.

公开(公告)号：US09711520B2

公开(公告)日：2017-07-18

申请号：US14735811

申请日：2015-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Etienne Nowak ,  Xia Zhiliang ,  Daesin Kim ,  Young-Gu Kim ,  Narae Jeong

IPC: H01L27/115 ,  H01L27/11573 ,  H01L27/11578 ,  G11C16/04 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/11582 ,  G11C8/14

CPC classification number: H01L27/11573 ,  G11C8/14 ,  G11C16/04 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/42344

Abstract: A semiconductor memory device includes a semiconductor substrate including a common source region and a drain region, a lower structure provided on the semiconductor substrate and including a plurality of lower transistors connected in series between the common source region and the drain region, a stack including a plurality of word lines stacked on the lower structure, and semiconductor pillars penetrating the stack and controlling gate electrodes of respective ones of the lower transistors.