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公开(公告)号:US20250104217A1
公开(公告)日:2025-03-27
申请号:US18784343
申请日:2024-07-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Bo Gyeong Kang , Ye Ji Kim , Min-Chul Park , Byoung Seon Choi , Seong Ryeol Kim , Young-Gu Kim , Jae Myung Choe
IPC: G06T7/00 , G06V10/44 , G06V10/75 , G06V10/762
Abstract: A computing device of predicting potential predicting potential defect-inducing factors within a semiconductor layout is provided. The computing device comprising: a machine learning module, calculating predicted measurement data corresponding to at least one first semiconductor layout image among a plurality of semiconductor layout mages after being trained based on the plurality of semiconductor layout images and corresponding real measurement data and an image explanation module generating an attribution map image of the predicted measurement data based on an image regression model utilizing an integrated gradient (IG) manner, analyzing the attribution map image and detecting elements within the attribution map image with attribution values with high sensitivity to the predicted measurement data as potential defect-inducing factors in advance.
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公开(公告)号:US10055829B2
公开(公告)日:2018-08-21
申请号:US15252613
申请日:2016-08-31
Applicant: Samsung Electronics Co., Ltd.
Inventor: Min-Chul Park , Je-Hyun Lee , Jeong-Hoon Ko , Young-Gu Kim , Keun-Ho Lee
CPC classification number: G06T7/0004 , G06T5/002 , G06T7/12 , G06T7/62 , G06T2207/10061 , G06T2207/20024 , G06T2207/20048 , G06T2207/20216 , G06T2207/30148
Abstract: A thickness of a first layer in a structure may be measured based on an original image of the structure. A first boundary of the first layer may be identified in the original image. A second boundary that is substantially indistinguishable in the original image may be identified based on converting the original image into a first image based on the first boundary and generating a second image based on filtering the first image. The first image may be generated based on adjusting partial image portions of the original image to align the representation of the first boundary with an axis line, such that the first image includes a representation of the first boundary that extends substantially in parallel with the axis line. The second boundary may be identified from the second image, and the thickness of the layer may be determined based on the identified first and second boundaries.
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公开(公告)号:US20170109896A1
公开(公告)日:2017-04-20
申请号:US15252613
申请日:2016-08-31
Applicant: Samsung Electronics Co., Ltd.
Inventor: Min-Chul Park , Je-Hyun Lee , Jeong-Hoon Ko , Young-Gu Kim , Keun-Ho Lee
CPC classification number: G06T7/0004 , G06T5/002 , G06T7/12 , G06T7/62 , G06T2207/10061 , G06T2207/20024 , G06T2207/20048 , G06T2207/20216 , G06T2207/30148
Abstract: A thickness of a first layer in a structure may be measured based on an original image of the structure. A first boundary of the first layer may be identified in the original image. A second boundary that is substantially indistinguishable in the original image may be identified based on converting the original image into a first image based on the first boundary and generating a second image based on filtering the first image. The first image may be generated based on adjusting partial image portions of the original image to align the representation of the first boundary with an axis line, such that the first image includes a representation of the first boundary that extends substantially in parallel with the axis line. The second boundary may be identified from the second image, and the thickness of the layer may be determined based on the identified first and second boundaries.
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公开(公告)号:US09711520B2
公开(公告)日:2017-07-18
申请号:US14735811
申请日:2015-06-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Etienne Nowak , Xia Zhiliang , Daesin Kim , Young-Gu Kim , Narae Jeong
IPC: H01L27/115 , H01L27/11573 , H01L27/11578 , G11C16/04 , H01L29/423 , H01L27/11565 , H01L27/11582 , G11C8/14
CPC classification number: H01L27/11573 , G11C8/14 , G11C16/04 , H01L27/11565 , H01L27/11578 , H01L27/11582 , H01L29/42344
Abstract: A semiconductor memory device includes a semiconductor substrate including a common source region and a drain region, a lower structure provided on the semiconductor substrate and including a plurality of lower transistors connected in series between the common source region and the drain region, a stack including a plurality of word lines stacked on the lower structure, and semiconductor pillars penetrating the stack and controlling gate electrodes of respective ones of the lower transistors.
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